Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

fix comment in entry.S #252

Open
wants to merge 1 commit into
base: riscv
Choose a base branch
from
Open

fix comment in entry.S #252

wants to merge 1 commit into from

Conversation

papparapa
Copy link

sp initially refers to the bottom of the stack allocated to each CPU.

echtwerner
echtwerner approved these changes Oct 7, 2024
View reviewed changes
Copy link

@echtwerner echtwerner left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This is correct.
register a1 contains the hartid and with "addi a1, a1, 1" instruction it is hartid +1..

This change should be approved.

echtwerner added a commit to echtwerner/xv6-riscv that referenced this pull request Oct 7, 2024
@echtwerner
fix: omment in entry.S
2f6964d 
This is a  manual change based on PR mit-pdos#252
@echtwerner
Copy link

I implemented the change in my PR #280, too.
But I did some other stiff in PR #280.
My line is "# sp = stack0 + ((hartid + 1) * CPUSTACKSIZE)"

@echtwerner echtwerner mentioned this pull request Oct 7, 2024
Open
@echtwerner
Copy link

PR#201 should be merge instead. Since the additonal comment line helps to clarify what is gooing on.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Reviewers

@echtwerner echtwerner echtwerner approved these changes

Assignees
No one assigned
Labels
None yet
Projects
None yet
Milestone
No milestone
Development

Successfully merging this pull request may close these issues.
2 participants
@papparapa @echtwerner