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[CHERRY-PICK] UefiCpuPkg/MpInitLib: Enable execute disable bit. #790
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makubacki
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microsoft:release/202311
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kenlautner:cherry_pick_mplib_fix
Apr 5, 2024
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[CHERRY-PICK] UefiCpuPkg/MpInitLib: Enable execute disable bit. #790
makubacki
merged 1 commit into
microsoft:release/202311
from
kenlautner:cherry_pick_mplib_fix
Apr 5, 2024
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This patch synchronizes the No-Execute bit in the IA32_EFER register for the APs before the RestoreVolatileRegisters operation. The commit 964a4f0, titled "Eliminate the second INIT-SIPI-SIPI sequence," replaces the second INIT-SIPI-SIPI sequence with the BSP calling the SwitchApContext function to initiate a specialized start-up signal, waking up APs in the DXE instead of using INIT-SIPI-SIPI. Due to this change, the logic for "Enable execute disable bit" in MpFuncs.nasm is no longer executed. However, to ensure the proper setup of the page table, it is necessary to synchronize the IA32_EFER.NXE for APs before executing RestoreVolatileRegisters . Based on SDM: If IA32_EFER.NXE is set to 1, it signifies execute-disable, meaning instruction fetches are not allowed from the 4-KByte page controlled by this entry. Conversely, if it is set to 0, it is reserved. Signed-off-by: Yuanhao Xie <[email protected]> Reviewed-by: Laszlo Ersek <[email protected]> Reviewed-by: Ray Ni <[email protected]> Cc: Laszlo Ersek [email protected] Cc: Eric Dong <[email protected]> Cc: Ray Ni <[email protected]> Cc: Rahul Kumar <[email protected]> Cc: Gerd Hoffmann <[email protected]>
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Apr 5, 2024
Note: Updated PR description to include cherry picked commit hash. |
makubacki
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Apr 5, 2024
kuqin12
approved these changes
Apr 5, 2024
ProjectMuBot
referenced
this pull request
in microsoft/mu_tiano_platforms
Apr 9, 2024
Introduces 3 new commits in [MU_BASECORE](https://github.com/microsoft/mu_basecore.git). <details> <summary>Commits</summary> <ul> <li><a href="https://github.com/microsoft/mu_basecore/commit/ad728a5b0ff40edd2598b2b8b4aa8e35a99ef349">ad728a</a> Updated LinuxCFLAGS to match the change made from edk2 (<a href="https://github.com/microsoft/mu_basecore/pull/789">#789</a>)</li> <li><a href="https://github.com/microsoft/mu_basecore/commit/7f1f52fc97152e4a2c333aea732b9c644560fd68">7f1f52</a> [CHERRY-PICK] UefiCpuPkg/MpInitLib: Enable execute disable bit. (<a href="https://github.com/microsoft/mu_basecore/pull/790">#790</a>)</li> <li><a href="https://github.com/microsoft/mu_basecore/commit/822b984a66116b1e4430980175ea497180bad85f">822b98</a> MdeModulePkg/MemoryProtectionSupport: Fix GCC type mismatch warnings (<a href="https://github.com/microsoft/mu_basecore/pull/791">#791</a>)</li> </ul> </details> Signed-off-by: Project Mu Bot <[email protected]>
kuqin12
referenced
this pull request
in microsoft/mu_tiano_platforms
Apr 9, 2024
Bumps MU_BASECORE from `2023110003.1.1` to `2023110003.1.2` Introduces 3 new commits in [MU_BASECORE](https://github.com/microsoft/mu_basecore.git). <details> <summary>Commits</summary> <ul> <li><a href="https://github.com/microsoft/mu_basecore/commit/ad728a5b0ff40edd2598b2b8b4aa8e35a99ef349">ad728a</a> Updated LinuxCFLAGS to match the change made from edk2 (<a href="https://github.com/microsoft/mu_basecore/pull/789">#789</a>)</li> <li><a href="https://github.com/microsoft/mu_basecore/commit/7f1f52fc97152e4a2c333aea732b9c644560fd68">7f1f52</a> [CHERRY-PICK] UefiCpuPkg/MpInitLib: Enable execute disable bit. (<a href="https://github.com/microsoft/mu_basecore/pull/790">#790</a>)</li> <li><a href="https://github.com/microsoft/mu_basecore/commit/822b984a66116b1e4430980175ea497180bad85f">822b98</a> MdeModulePkg/MemoryProtectionSupport: Fix GCC type mismatch warnings (<a href="https://github.com/microsoft/mu_basecore/pull/791">#791</a>)</li> </ul> </details> Signed-off-by: Project Mu Bot <[email protected]>
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Description
This patch synchronizes the No-Execute bit in the IA32_EFER register for the APs before the RestoreVolatileRegisters operation.
The commit 964a4f0, titled "Eliminate the second INIT-SIPI-SIPI sequence," replaces the second INIT-SIPI-SIPI sequence with the BSP calling the SwitchApContext function to initiate a specialized start-up signal, waking up APs in the DXE instead of using INIT-SIPI-SIPI.
Due to this change, the logic for "Enable execute disable bit" in MpFuncs.nasm is no longer executed. However, to ensure the proper setup of the page table, it is necessary to synchronize the IA32_EFER.NXE for APs before executing RestoreVolatileRegisters.
Based on SDM:
If IA32_EFER.NXE is set to 1, it signifies execute-disable, meaning instruction fetches are not allowed from the 4-KByte page controlled by this entry. Conversely, if it is set to 0, it is reserved.
Reviewed-by: Laszlo Ersek [email protected]
Reviewed-by: Ray Ni [email protected]
Cc: Laszlo Ersek [email protected]
Cc: Eric Dong [email protected]
Cc: Ray Ni [email protected]
Cc: Rahul Kumar [email protected]
Cc: Gerd Hoffmann [email protected]
(cherry picked from commit cb3f41a)
flow, or firmware?
validation improvement, ...
in build or boot behavior?
a function in a new library class in a pre-existing module, ...
outside direct code modifications (and comments)?
on an a separate Web page, ...