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DCCM stall issue resolved
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@AbdulRauf-Sidd
AbdulRauf-Sidd committed Sep 5, 2024
1 parent 7e5afff commit bcf0474
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Showing 2 changed files with 139 additions and 19 deletions.
146 changes: 129 additions & 17 deletions src/main/scala/components/Core.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,7 @@ class Core(implicit val config:Configs) extends Module{

val fcsr_o_data = Output(UInt(32.W))
})

val dccm_stall = WireInit(0.B)
// IF-ID Registers
val if_reg_pc = RegInit(0.U(32.W))
val if_reg_ins = RegInit(0.U(32.W))
Expand Down Expand Up @@ -156,23 +156,28 @@ class Core(implicit val config:Configs) extends Module{
IF.stall := io.stall || EX.stall || ID.stall || IF_stall //stall signal from outside

// pc.io.halt := Mux(io.imemReq.valid || ~EX.stall || ~ID.stall, 0.B, 1.B)
pc.io.halt := Mux(((EX.stall || ID.stall || IF_stall || ~io.imemReq.valid) | ral_halt_o), 1.B, 0.B)
pc.io.halt := Mux(((EX.stall || ID.stall || IF_stall || ~io.imemReq.valid || dccm_stall) | ral_halt_o), 1.B, 0.B)
val npc = Mux(ID.hdu_pcWrite, Mux(ID.pcSrc, ID.pcPlusOffset.asSInt(), Mux(is_comp, pc.io.pc2, pc.io.pc4)), pc.io.out)
pc.io.in := npc

when(ID.hdu_if_reg_write) {
if_reg_pc := pc.io.out.asUInt()
if_reg_ins := instruction
}
when(ID.ifid_flush) {
if_reg_ins := 0.U
}

when(!dccm_stall){
when(ID.hdu_if_reg_write) {
if_reg_pc := pc.io.out.asUInt()
if_reg_ins := instruction
}
when(ID.ifid_flush) {
if_reg_ins := 0.U
}
}
.otherwise{
if_reg_ins := if_reg_ins
if_reg_pc := if_reg_pc
}

/****************
* Decode Stage *
****************/

when(!dccm_stall){
id_reg_rd1 := ID.readData1
id_reg_rd2 := ID.readData2
id_reg_imm := ID.immediate
Expand All @@ -192,6 +197,28 @@ class Core(implicit val config:Configs) extends Module{
id_reg_ctl_aluSrc1 := ID.ctl_aluSrc1
id_reg_is_csr := ID.is_csr
id_reg_csr_data := ID.csr_o_data
}.otherwise{
id_reg_rd1 := id_reg_rd1
id_reg_rd2 := id_reg_rd2
id_reg_imm := id_reg_imm
id_reg_wra := id_reg_wra
id_reg_f3 := id_reg_f3
id_reg_f7 := id_reg_f7
id_reg_ins := id_reg_ins
id_reg_pc := id_reg_pc
id_reg_ctl_aluSrc := id_reg_ctl_aluSrc
id_reg_ctl_memToReg := id_reg_ctl_memToReg
id_reg_ctl_regWrite := id_reg_ctl_regWrite
id_reg_ctl_memRead := id_reg_ctl_memRead
id_reg_ctl_memWrite := id_reg_ctl_memWrite
id_reg_ctl_branch := id_reg_ctl_branch
id_reg_ctl_aluOp := id_reg_ctl_aluOp
id_reg_ctl_jump := id_reg_ctl_jump
id_reg_ctl_aluSrc1 := id_reg_ctl_aluSrc1
id_reg_is_csr := id_reg_is_csr
id_reg_csr_data := id_reg_csr_data
// IF.PcWrite := ID.hdu_pcWrite
}
// IF.PcWrite := ID.hdu_pcWrite
ID.id_instruction := if_reg_ins
ID.pcAddress := if_reg_pc
Expand All @@ -208,6 +235,43 @@ class Core(implicit val config:Configs) extends Module{
ID.id_ex_regWr := id_reg_ctl_regWrite
ID.ex_mem_regWr := ex_reg_ctl_regWrite

// .otherwise{
// id_reg_rd1 := id_reg_rd1
// id_reg_rd2 := id_reg_rd2
// id_reg_imm := id_reg_imm
// id_reg_wra := ID.writeRegAddress
// id_reg_f3 := ID.func3
// id_reg_f7 := ID.func7
// id_reg_ins := if_reg_ins
// id_reg_pc := if_reg_pc
// id_reg_ctl_aluSrc := ID.ctl_aluSrc
// id_reg_ctl_memToReg := ID.ctl_memToReg
// id_reg_ctl_regWrite := ID.ctl_regWrite
// id_reg_ctl_memRead := ID.ctl_memRead
// id_reg_ctl_memWrite := ID.ctl_memWrite
// id_reg_ctl_branch := ID.ctl_branch
// id_reg_ctl_aluOp := ID.ctl_aluOp
// id_reg_ctl_jump := ID.ctl_jump
// id_reg_ctl_aluSrc1 := ID.ctl_aluSrc1
// id_reg_is_csr := ID.is_csr
// id_reg_csr_data := ID.csr_o_data
// // IF.PcWrite := ID.hdu_pcWrite
// ID.id_instruction := if_reg_ins
// ID.pcAddress := if_reg_pc
// ID.dmem_resp_valid := io.dmemRsp.valid
// // IF.PcSrc := ID.pcSrc
// // IF.PCPlusOffset := ID.pcPlusOffset
// ID.ex_ins := id_reg_ins
// ID.ex_mem_ins := ex_reg_ins
// ID.mem_wb_ins := mem_reg_ins
// ID.ex_mem_result := ex_reg_result

// ID.csr_i_misa := DontCare
// ID.csr_i_mhartid := DontCare
// ID.id_ex_regWr := id_reg_ctl_regWrite
// ID.ex_mem_regWr := ex_reg_ctl_regWrite
// }

/*****************
* Execute Stage *
******************/
Expand All @@ -225,6 +289,8 @@ class Core(implicit val config:Configs) extends Module{
EX.ctl_aluSrc := id_reg_ctl_aluSrc
EX.ctl_aluOp := id_reg_ctl_aluOp
EX.ctl_aluSrc1 := id_reg_ctl_aluSrc1

when (!dccm_stall) {
//EX.ctl_branch := id_reg_ctl_branch
//EX.ctl_jump := id_reg_ctl_jump
ex_reg_pc := id_reg_pc
Expand All @@ -236,6 +302,17 @@ class Core(implicit val config:Configs) extends Module{
ex_reg_csr_data := id_reg_csr_data
// ex_reg_ctl_memRead := id_reg_ctl_memRead
// ex_reg_ctl_memWrite := id_reg_ctl_memWrite
}.otherwise{
ex_reg_pc := ex_reg_pc
ex_reg_wra := ex_reg_wra
ex_reg_ins := ex_reg_ins
ex_reg_ctl_memToReg := ex_reg_ctl_memToReg
ex_reg_ctl_regWrite := ex_reg_ctl_regWrite
ex_reg_is_csr := ex_reg_is_csr
ex_reg_csr_data := ex_reg_csr_data
// ex_reg_ctl_memRead := id_reg_ctl_memRead
// ex_reg_ctl_memWrite := id_reg_ctl_memWrite
}
ID.id_ex_mem_read := id_reg_ctl_memRead
ID.ex_mem_mem_read := ex_reg_ctl_memRead
// ID.ex_mem_mem_write := ex_reg_ctl_memWrite
Expand All @@ -256,12 +333,18 @@ class Core(implicit val config:Configs) extends Module{
id_reg_ctl_regWrite := id_reg_ctl_regWrite
}

when(EX.stall){
id_reg_wra := id_reg_wra
id_reg_ctl_regWrite := id_reg_ctl_regWrite
}

/****************
* Memory Stage *
****************/

io.dmemReq <> MEM.io.dccmReq
MEM.io.dccmRsp <> io.dmemRsp
dccm_stall := MEM.io.stall
// val stall = Wire(Bool())
// stall := (ex_reg_ctl_memWrite || ex_reg_ctl_memRead) && !io.dmemRsp.valid
// when(MEM.io.stall){
Expand All @@ -282,6 +365,8 @@ class Core(implicit val config:Configs) extends Module{
//// ex_reg_result := 0.U
//
// } otherwise{

when(!dccm_stall) {
mem_reg_rd := MEM.io.readData
mem_reg_result := ex_reg_result
// mem_reg_ctl_memToReg := ex_reg_ctl_memToReg
Expand All @@ -294,10 +379,29 @@ class Core(implicit val config:Configs) extends Module{
ex_reg_wd := EX.writeData
ex_reg_result := EX.ALUresult
// }
mem_reg_wra := ex_reg_wra
mem_reg_ctl_memToReg := ex_reg_ctl_memToReg
mem_reg_is_csr := ex_reg_is_csr
mem_reg_csr_data := ex_reg_csr_data
mem_reg_wra := ex_reg_wra
mem_reg_ctl_memToReg := ex_reg_ctl_memToReg
mem_reg_is_csr := ex_reg_is_csr
mem_reg_csr_data := ex_reg_csr_data

}.otherwise{
mem_reg_rd := mem_reg_rd
mem_reg_result := mem_reg_result
// mem_reg_ctl_memToReg := ex_reg_ctl_memToReg
mem_reg_ctl_regWrite := mem_reg_ctl_regWrite
mem_reg_ins := mem_reg_ins
mem_reg_pc := mem_reg_pc
mem_reg_wra := mem_reg_wra
ex_reg_ctl_memRead := ex_reg_ctl_memRead
ex_reg_ctl_memWrite := ex_reg_ctl_memWrite
ex_reg_wd := ex_reg_wd
ex_reg_result := ex_reg_result
// }
mem_reg_wra := mem_reg_wra
mem_reg_ctl_memToReg := mem_reg_ctl_memToReg
mem_reg_is_csr := mem_reg_is_csr
mem_reg_csr_data := mem_reg_csr_data
}
EX.ex_mem_regWrite := ex_reg_ctl_regWrite
MEM.io.aluResultIn := ex_reg_result
MEM.io.writeData := ex_reg_wd
Expand Down Expand Up @@ -327,6 +431,15 @@ class Core(implicit val config:Configs) extends Module{
wb_addr := mem_reg_wra
}


//when (!dccm_stall) {
// io.pin := wb_data
//}.otherwise{
// io.pin := io.pin
//}

io.pin := wb_data

ID.mem_wb_result := wb_data
ID.writeData := wb_data
EX.wb_result := wb_data
Expand All @@ -336,7 +449,6 @@ class Core(implicit val config:Configs) extends Module{
ID.csr_Wb := mem_reg_is_csr
ID.csr_Wb_data := mem_reg_csr_data
ID.dmem_data := io.dmemRsp.bits.dataResponse
io.pin := wb_data

/**************
** RVFI PINS **
Expand Down Expand Up @@ -398,4 +510,4 @@ class Core(implicit val config:Configs) extends Module{
tr => tr._1 := tr._2
)
}
}
}
12 changes: 10 additions & 2 deletions src/main/scala/components/MemoryFetch.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -91,11 +91,19 @@ class MemoryFetch extends Module {
io.dccmReq.bits.activeByteLane := "b1111".U
}

//val reqvalid = WireInit(0.B)

io.dccmReq.bits.dataRequest := wdata.asUInt()
io.dccmReq.bits.addrRequest := (io.aluResultIn & "h00001fff".U) >> 2
io.dccmReq.bits.isWrite := io.writeEnable
io.dccmReq.valid := Mux(io.writeEnable | io.readEnable, true.B, false.B)

when(io.stall) {
io.dccmRsp.ready := false.B
}.otherwise {
io.dccmRsp.ready := true.B
}

io.dccmReq.valid := Mux(io.writeEnable | io.readEnable, true.B, false.B)
io.stall := (io.writeEnable || io.readEnable) && !io.dccmRsp.valid

rdata := Mux(io.dccmRsp.valid, io.dccmRsp.bits.dataResponse, DontCare)
Expand Down Expand Up @@ -185,7 +193,7 @@ class MemoryFetch extends Module {
}


when(io.writeEnable && io.aluResultIn(31, 28) === "h8".asUInt()){
when(io.writeEnable && ~io.stall){
printf("%x\n", io.writeData)
}

Expand Down

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