Add I/O timing cons, fix speed-grade, faster JTAG

- Add I/O timing constraints for all ports.
- Correct FPGA speed-grade to the faster "-2" grade.
- Increase openocd JTAG speed using on-board programmer
  (used when loading programs into SRAM from computer).
- Add missing HyperRAM physical IOB constraint.
- Tidy pins_sonata.xdc and update deprecated properties.

The biggest change (by volume) is by far the I/O timing constraints.
These should improve timing on some synchronous interfaces,
such as the User JTAG, and improve reliability.
Further changes/refinements are likely.
Note that internal timing constraints have yet to be tackled.

Also note that build times may increase slightly due the there being
more for the tool to consider and optimise timing-wise.