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Update OT Darjeeling support #62

Merged
merged 37 commits into from
May 7, 2024
Merged

Update OT Darjeeling support #62

merged 37 commits into from
May 7, 2024

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rivos-eblot
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  • Initial I2C support
  • Improved JTAG/DTM/DM Python modules
  • All Python modules are now Pylint-ed
  • Fix guest clock (-icount N is now muh more accurate)
  • Initial SRAM controller with SRAM content init and scrambling
  • Fix Ibex core definitions (MISA & extension support are now accurate)
  • Update HW definitions

rivos-eblot and others added 30 commits May 7, 2024 20:31
@rivos-eblot
[ot] .gitlab-ci.d: update BM tests: wait for LC DMI to get up and run…
8648fdb 
…ning

Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] .gitlab-ci.d: update configuration files
fad0298 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] .gitlab-ci.d: update BM tests: refactor test files
ea6463f 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] hw/opentitan: update mailbox registers following latest RTL update
481a749 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] .gitlab-ci.d: update BM tests: update for new mailbox register map
322a4b1 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] hw/core: loader.c: extends ELF loader API to opt. skip empty sec…
309b957 
…tion space.

Default QEMU behavior is to zero-initialize parts of sections that are not
stored in the ELF file. For embedded SW, sections such as `.bss` should not
be initialized by the loader, but at runtime: destination memory may not be
available / reachable at QEMU load time.

Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] hw/opentitan: ot_rom_ctrl: do not initialize NOBITS sections
e82d42b 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] hw/opentitan: ot_otp_dj: allocate sub structures outside main OTP
4ef9a43 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] hw/opentitan: ot_otp_dj: add initial support for SRAM scrambling
512ff99 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] hw/opentitan: ot_sram_ctrl: add support for init and scrambling
170c150 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] hw/opentitan: ot_dev_proxy: improve SRAM controller support
75725f2 
DevProxy needs to access both the RAM and the control registers.

Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] hw/opentitan: ot_rom_ctrl: demangle Rust symbol when loading ELF
e554874 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] scripts/opentitan: pyot.py: add support to execute from ROM(s)
0d0ab68 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] hw/riscv: ibex_common: update ibex_load_kernel API
4873023 
It is now possible to define, through the machine, if the vCPU(s) PC
are updated with the ELF entry point address, thanks to a new boolean
property 'ignore-elf-entry'.

Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] hw/riscv: ot_earlgrey, ot_darjeeling: implement ignore-elf-entry…
2bd4b13 
… prop.

Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] .gitlab-ci.d: update BM tests: execute tests from ROM
d749653 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] scripts/opentitan: address remaining pylint issues
1923ce5 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] .gitlab-ci.d: enable Python linter on all OT scripts and modules
271ec81 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] hw/riscv: ot_darjeeling: update clocks.
425afc2 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] .gitlab-ci.d: update BM tests for new clock settings
6300861 
Signed-off-by: Emmanuel Blot <[email protected]>
@loiclefort @rivos-eblot
[ot] target/riscv: add static Ibex CPU configs
80f5fef 
QEMU enables several RISC-V extensions on dynamic CPUs that require explicit
deactivation in custom cpu init functions.
This commit creates two static CPU configurations for the actual Ibex CPU
instances used: Ibex Demo and OpenTitan. The dynamic Ibex configuration will be
removed in a later commit.

Signed-off-by: Loïc Lefort <[email protected]>
@loiclefort @rivos-eblot
[ot] hw/riscv: switch to static Ibex CPU configs
4b87bad 
Signed-off-by: Loïc Lefort <[email protected]>
@loiclefort @rivos-eblot
[ot] target/riscv: remove dynamic Ibex CPU configuration
4427d8d 
Signed-off-by: Loïc Lefort <[email protected]>
@rivos-eblot
[ot] .gitlab-ci.d: update BM tests for Ibex MISA definition
839ad5b 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] hw/opentitan: ot_i2c_dj: add I2C driver for Darjeeling
fe7c273 
Add a driver for the OpenTitan I2C Darjeeling controller that supports
host and target mode.

Signed-off-by: Duncan Laurie <[email protected]>
@rivos-eblot
[ot] hw/riscv: add I2C controller to OpenTitan Darjeeling
2e77c61 
- configure the I2C instance in ot_darjeeling platform.

Signed-off-by: Duncan Laurie <[email protected]>
@rivos-eblot
Revert "[ot] target/riscv: trans_privileged: handle WFI as NOP when s…
50eece7 
…ingle stepping"

This reverts commit b8c4153.

Testing ctx->cs->exception_index here makes no sense since this is part
of guest code generation, not execution.

Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] scripts/opentitan: pyot.py: double-error fix
53a92b1 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] hw/opentitan: ot_soc_proxy: fix line width
94b0c8d 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] hw/opentitan: ot_rstmgr: use ot_id in traces
490b0cb 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] hw/opentitan: ot_pwrmgr: update with latest reverse engineering …
1420b1f 
…session

Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] hw/opentitan: ot_spi_host: add ot_id device identifier
cbc38c8 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] hw/opentitan: ot_spi_host: fix invalid aperture
9a844aa 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] hw/misc: unimp: add an option to only warn once on each access type
28e8614 
The option is disabled by default.

Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] hw/opentitan: use parent name when ot_id is not defined.
28151a2 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] hw/opentitan: trace-events: sort trace function by file, func name
04ad4b6 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] .gitlab-ci.d: make pylint runs in build rather than test stage.
ff0ef1a 
Signed-off-by: Emmanuel Blot <[email protected]>
loiclefort
loiclefort approved these changes May 7, 2024
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LGTM (already reviewed and tested at Rivos)

@rivos-eblot rivos-eblot merged commit 060bca8 into lowRISC:ot-darjeeling-8.2.0 May 7, 2024
5 checks passed
@rivos-eblot rivos-eblot deleted the dev/ebl/dj_resync branch May 7, 2024 18:44
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@rivos-eblot @loiclefort