Tests failing when running regression using Questa

[bekbeis]

Issue Description

Hi!

I'm trying to achieve regression results close to the ones described in the nightly report locally. Several tests are showing a 0% pass rate. I've listed them below along with the associated error messages.

• riscv_debug_instr_test
  • [E] 186: # UVM_FATAL /home/maveric/cores/IBEX/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 1994048729: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: ffffffff800123e0 but the DUT didn't report one at PC 800123dc
• riscv_debug_wfi_test
  • [E] 114: # UVM_FATAL /home/maveric/cores/IBEX/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 95248729: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: ffffffff8000393e but the DUT didn't report one at PC 8000393a
• riscv_interrupt_wfi_test
  • [E] 114: # UVM_FATAL /home/maveric/cores/IBEX/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 123288729: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: ffffffff80003ae6 but the DUT didn't report one at PC 80003ae2
• riscv_pc_intg_test
  • 119: # ** Error (suppressible): (vsim-16132) Unable to read value from 'core_ibex_tb_top.dut.u_ibex_top.u_ibex_core.core_busy_o' Either the path is incorrect, or you may not have PLI/ACC visibility to that object. [E] 120: # UVM_FATAL /home/maveric/cores/IBEX/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(39) @ 22209644: reporter [uvm_test_top] Check failed (uvm_hdl_read(core_busy_path, core_busy))
• riscv_rf_ctrl_intg_test
  • 120: # ** Error (suppressible): (vsim-16132) Unable to read value from 'core_ibex_tb_top.dut.u_ibex_top.alert_major_internal_o' Either the path is incorrect, or you may not have PLI/ACC visibility to that object. [E] 121: # UVM_FATAL /home/maveric/cores/IBEX/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(256) @ 144938729: reporter [uvm_test_top] Check failed (uvm_hdl_read(alert_major_internal_path, alert_major_internal))
• riscv_ram_intg_test
  • 115: # ** Error (suppressible): (vsim-16132) Unable to read value from 'core_ibex_tb_top.dut.u_ibex_top.gen_rams.gen_rams_inner[0].gen_scramble_rams.data_bank.u_prim_ram_1p_adv.req_q' Either the path is incorrect, or you may not have PLI/ACC visibility to that object. [E] 116: # UVM_FATAL /home/maveric/cores/IBEX/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(354) @ 59178729: reporter [uvm_test_top] Check failed (uvm_hdl_read(glitch_path, orig_val))
• riscv_rf_intg_test
  • [FAILED]: Processing the ibex trace failed: Logfile /home/maveric/cores/IBEX/ibex/dv/uvm/core_ibex/out/run/tests/riscv_rf_intg_test.25036/trace_core_00000000.log not found
• riscv_icache_intg_test
  • [FAILED]: Processing the ibex trace failed: Logfile /home/maveric/cores/IBEX/ibex/dv/uvm/core_ibex/out/run/tests/riscv_icache_intg_test.25031/trace_core_00000000.log not found

Can you please share any ideas on what might be wrong and how I can fix these issues?
The tests were run using the make --keep-going IBEX_CONFIG=opentitan SIMULATOR=questa ISS=spike WAVES=0 COV=0 command. I am also attaching the log file. Please let me know if you need any additional information.

regr.log

Thank you in advance for any guidance you can provide.

My Environment

EDA tool and version: Siemens Questa Sim-64 2024.1_2

Operating system: Ubuntu 22.04.4 LTS

Version of the Ibex source code: 3937e48
I also had to make several adjustments, including some mentioned in this issue, to be able to run everything with Questa. Here is the list of all modified files:

• dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv
• dv/uvm/core_ibex/fcov/core_ibex_pmp_fcov_if.sv
• dv/uvm/core_ibex/riscv_dv_extension/ibex_log_to_trace_csv.py
• dv/uvm/core_ibex/riscv_dv_extension/riscv_core_setting.tpl.sv
• dv/uvm/core_ibex/scripts/run_instr_gen.py
• dv/uvm/core_ibex/yaml/rtl_simulation.yaml
• rtl/ibex_tracer.sv
• vendor/google_riscv-dv/yaml/simulator.yaml