Spike not generating csrrw and compressed instructions

[yuhbj]

Running RTL simulation at out/seed-6496/rtl_sim/riscv_illegal_instr_test.6496/sim.log
Comparing traces for out/seed-6496/rtl_sim/riscv_illegal_instr_test.6496
Collecting up results (report at out/seed-6496/regr.log)
0.00% PASS 0 PASSED, 1 FAILED
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Details of failing tests

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riscv_illegal_instr_test.6496

Test binary: out/seed-6496/instr_gen/asm_test/riscv_illegal_instr_test_0.o
UVM log: out/seed-6496/rtl_sim/riscv_illegal_instr_test.6496/sim.log
RTL trace: out/seed-6496/rtl_sim/riscv_illegal_instr_test.6496/trace_core_00000000.log

** Note: (vsim-12126) Error and warning message counts have been restored: Errors=0, Warnings=43.

[FAILED]: sim error seen

0.00% PASS 0 PASSED, 1 FAILED