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Allow display code to work when debugging ARM binaries. #169

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Allow display code to work when debugging ARM binaries. #169

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56c8d6d
Allow display code to work when debugging ARM binaries.
ZenClark Sep 5, 2021
7a39905
Fixing a change that got reverted at some point.
ZenClark Sep 6, 2021
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39 changes: 27 additions & 12 deletions peda.py
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Original file line number Diff line number Diff line change
Expand Up @@ -18,6 +18,7 @@
import signal
import traceback
import codecs
import platform

# point to absolute path of peda.py
PEDAFILE = os.path.abspath(os.path.expanduser(__file__))
Expand Down Expand Up @@ -51,13 +52,25 @@
from urllib import urlencode
pyversion = 2

REGISTERS = {
8 : ["al", "ah", "bl", "bh", "cl", "ch", "dl", "dh"],
16: ["ax", "bx", "cx", "dx"],
32: ["eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp", "eip"],
64: ["rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp", "rip",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"]
}
REGISTERS = {}

PLATFORM = platform.machine()

if "arm" in PLATFORM:

REGISTERS = {
32: ["r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9"]
}

else:

REGISTERS = {
8 : ["al", "ah", "bl", "bh", "cl", "ch", "dl", "dh"],
16: ["ax", "bx", "cx", "dx"],
32: ["eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp", "eip"],
64: ["rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp", "rip",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"]
}

###########################################################################
class PEDA(object):
Expand Down Expand Up @@ -753,7 +766,7 @@ def disassemble(self, *arg):
if len(arg) == 1 and to_int(arg[0]) != None:
arg += [to_hex(to_int(arg[0]) + 32)]

self.execute("set disassembly-flavor intel")
#self.execute("set disassembly-flavor intel")
out = self.execute_redirect("disassemble %s %s" % (modif, ",".join(arg)))
if not out:
return None
Expand Down Expand Up @@ -4247,7 +4260,9 @@ def context_register(self, *arg):
"""
if not self._is_running():
return


(arch, bits) = peda.getarch()

pc = peda.getreg("pc")
# display register info
msg("[%s]" % "registers".center(78, "-"), "blue")
Expand Down Expand Up @@ -4353,7 +4368,6 @@ def context(self, *arg):
Usage:
MYNAME [reg,code,stack,all] [code/stack length]
"""

(opt, count) = normalize_argv(arg, 2)

if to_int(count) is None:
Expand Down Expand Up @@ -4849,7 +4863,7 @@ def get_reg_text(r, v):
text += get_reg_text(r, v)
if text:
msg(text.strip())
if regname is None or "eflags" in regname:
if (regname is None or "eflags" in regname) and "arm" not in PLATFORM:
self.eflags()
return

Expand Down Expand Up @@ -6155,7 +6169,8 @@ def sigint_handler(signal, frame):
peda.execute("set height 0") # disable paging
peda.execute("set history expansion on")
peda.execute("set history save on") # enable history saving
peda.execute("set disassembly-flavor intel")
if "arm" not in PLATFORM:
peda.execute("set disassembly-flavor intel")
peda.execute("set follow-fork-mode child")
peda.execute("set backtrace past-main on")
peda.execute("set step-mode on")
Expand Down