Firtool Release 1.72.0

I messed up https://github.com/llvm/circt/releases/tag/firtool-1.71.0, sorry! This contains the correct (and many repeated) commits.

What's Changed

• [NFC] Move 'using namespace' out of headers. by @fzi-hielscher in #6844
• [FSM][Emit] Convert the FSMToSV pass to use emit ops by @nandor in #6828
• [Emit][Seq] Emit random init headers using fragments by @nandor in #6826
• [HW][IST] Verify simple inner-ref-user ops sequentially, perf fix. by @dtzSiFive in #6850
• Fix a few FileCheck directive typos. by @dtzSiFive in #6853
• [FIRRTL][NFC] Move xmr.ref and xmr.deref into expressions. by @dtzSiFive in #6852
• [circt-lec] Add ConstructLEC pass by @maerhart in #6833
• StripDebugInfoWithPred: Fix parallelization perf issue. by @dtzSiFive in #6851
• [ImportVerilog] Add if and loop statements by @fabianschuiki in #6831
• [FIRRTL] Remove support for circt.Intrinsic annotation. by @dtzSiFive in #6857
• [FIRRTL] Make "intrinsic" name of intmodule mandatory. by @dtzSiFive in #6858
• [Docs] Extend formal verification documentation by @maerhart in #6854
• [Seq] Erase memories with no read ports by @nandor in #6861
• [ImportVerilog] Add assign and pre/post increment/decrement expressions by @fabianschuiki in #6859
• [SMT] Add quantifier operations by @maerhart in #6842
• [SMT] Add function application operation, function and uninterpreted sort types by @maerhart in #6847
• [SV][Verif] Extract verif ops in SVExtractTestCode by @seldridge in #6865
• [NFCI] Declare common attributes for fmodule* by @darthscsi in #6868
• [FIRRTL] Cache a symbol table instead of doing linear lookups every instance. by @darthscsi in #6871
• [LowerToHW] Set fragments outside the parallel region by @nandor in #6872
• [SMT] Add SMT-LIB export translation by @maerhart in #6870
• [FIRRTL] Add generic intrinsic op. by @dtzSiFive in #6874
• [FIRRTL] Add LowerIntmodules pass. by @dtzSiFive in #6876
• [FIRRTL] Change Port Direction attribute from an APInt to a DenseArray. by @darthscsi in #6875
• [FIRRTL] Add intrinsic for UNR only assume by @uenoku in #6867
• [FIRRTL] Add CreateCompanionAssume pass; Decouple UNROnlyAssume generation from AssertOp lowering by @uenoku in #6863
• [NFC] Make fewer copies of directions by @darthscsi in #6879
• [Docs] GettingStarted: Fix images and LLVM/MLIR contributing guide by @ubfx in #6873
• [FIRRTL] Deprecate AssertAssume intrinsic and rename it to Assert by @uenoku in #6878
• [Docs] Correct a typo in circt-lec/README.md by @felixonmars in #6849
• [FIRRTL] Treat blackboxes in layers as "testbench" by @seldridge in #6881
• [SeqToSV] Fix the ordering of the memory/register random init fragments by @nandor in #6883
• [NFC] Massive Export Verilog Speedup by @darthscsi in #6886
• [LowerToHW] Emission Option for verification flavors by @uenoku in #6885
• [FIRRTL] Expose clock dividers as a FIRRTL intrinsic by @nandor in #6890
• [CFToHandshake] Move Transforms dependency to implementation by @mortbopet in #6889
• [NFC] Cache common lookups in ModuleType by @darthscsi in #6892

New Contributors

• @ubfx made their first contribution in #6873
• @felixonmars made their first contribution in #6849

Full Changelog: firtool-1.70.0...firtool-1.72.0