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[Seq] Add a pass to implement firreg randomization #7606

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@uenoku uenoku commented Sep 18, 2024

This pass performs firreg random initialization for seq.compreg. With this pass we can represent
firreg initialization with compreg so we can eventually deprecate existing FirregLowering. There are still
several differences:

  • Initialization for async reset registers is currently not fully implemented. This requires a change for seq.initial to capture port values to the body
  • Several macros are deprecated: FIRRTL_BEFORE_INITIAL, FIRRTL_AFTER_INITIAL

This pass has an option to generate the randomization as MLIR core dialects which
make it possible to simulate with arcilator. When emitSV is true, the pass generates
a random function call as a macro in the SV dialect. It supports configurable initialization of
registers through macros like RANDOM and INIT_RANDOM_PROLOG. If the option is false,
it produces simulatable IR using MLIR core dialects.

eg:

hw.module @top(in %clk: !seq.clock, in %rst: i1, in %i: i18, out o: i18, out j: i18) {
  %c0_i18 = hw.constant 0 : i18
  %r0 = seq.compreg %i, %clk reset %rst, %c0_i18 : i18
  %r1 = seq.compreg %i, %clk : i18

  hw.output %r0, %r1: i18, i18
}
circt-opt --pass-pipeline='builtin.module(seq-firreg-randomization{emit-sv=true},lower-seq-to-sv,canonicalize,export-verilog)'
module top(	// bar.mlir:4:1
  input         clk,	// bar.mlir:4:19
                rst,	// bar.mlir:4:40
  input  [17:0] i,	// bar.mlir:4:53
  output [17:0] o,	// bar.mlir:4:66
                j	// bar.mlir:4:78
);

  reg [17:0] r1;	// bar.mlir:7:9
  reg [17:0] r0;	// bar.mlir:6:9
  initial begin	// bar.mlir:4:1
    automatic logic [31:0] _GEN = `RANDOM;	// bar.mlir:4:1
    automatic logic [31:0] _GEN_0 = `RANDOM;	// bar.mlir:4:1
    `INIT_RANDOM_PROLOG_	// bar.mlir:4:1
    r0 = _GEN[17:0];	// bar.mlir:4:1, :6:9
    r1 = {_GEN[31:18], _GEN_0[3:0]};	// bar.mlir:4:1, :7:9
  end // initial
  always_ff @(posedge clk) begin	// bar.mlir:6:9
    if (rst)	// bar.mlir:6:9
      r0 <= 18'h0;	// bar.mlir:6:9
    else	// bar.mlir:6:9
      r0 <= i;	// bar.mlir:6:9
  end // always_ff @(posedge)
  always_ff @(posedge clk)	// bar.mlir:7:9
    r1 <= i;	// bar.mlir:7:9
  assign o = r0;	// bar.mlir:6:9, :30:3
  assign j = r1;	// bar.mlir:7:9, :30:3
endmodule

(RANDOM must not be placed before INIT_RANDOM_PROLOG_ so this is a bug of ExportVerilog)

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