[FIRRTL] Strict Instance Operation

include/circt/Dialect/FIRRTL/FIRRTLDeclarations.td

@@ -160,6 +160,128 @@ def InstanceOp : HardwareDeclOp<"instance", [
  let hasVerifier = true;
 }
 
+def StrictInstanceOp : HardwareDeclOp<"strictinstance", [
+ DeclareOpInterfaceMethods<FInstanceLike>,
+ DeclareOpInterfaceMethods<SymbolUserOpInterface>,
+ DeclareOpInterfaceMethods<InstanceGraphInstanceOpInterface, [
+ "getModuleName"
+ ]>,
+ ]> {
+ let summary = "Instantiate an instance of a module";
+ let description = [{
+ This represents an instance of a module. The results are the modules inputs
+ and outputs. The inputs have LHSType wrapped types, the outputs do not.
+
+ Examples:
+ ```mlir
+ %0 = firrtl.strictinstance foo @Foo(in io: !firrtl.uint)
+ firrtl.strictconnect %0, %c0_ui
+ ```
+ }];
+
+ let arguments = (ins FlatSymbolRefAttr:$moduleName, StrAttr:$name, NameKindAttr:$nameKind,
+ DenseBoolArrayAttr:$portDirections, StrArrayAttr:$portNames,
+ AnnotationArrayAttr:$annotations,
+ PortAnnotationsAttr:$portAnnotations,
+ LayerArrayAttr:$layers,
+ UnitAttr:$lowerToBind,
+ OptionalAttr<InnerSymAttr>:$inner_sym);
+
+ let results = (outs Variadic<AnyType>:$results);
+
+ let hasCustomAssemblyFormat = 1;
+
+ let builders = [
+ OpBuilder<(ins "::mlir::TypeRange":$resultTypes,
+ "::mlir::StringRef":$moduleName,
+ "::mlir::StringRef":$name,
+ "::circt::firrtl::NameKindEnum":$nameKind,
+ "::mlir::ArrayRef<Direction>":$portDirections,
+ "::mlir::ArrayRef<Attribute>":$portNames,
+ CArg<"ArrayRef<Attribute>", "{}">:$annotations,
+ CArg<"ArrayRef<Attribute>", "{}">:$portAnnotations,
+ CArg<"::mlir::ArrayRef<Attribute>", "{}">:$layers,
+ CArg<"bool","false">:$lowerToBind,
+ CArg<"StringAttr", "StringAttr()">:$innerSym)>,
+ OpBuilder<(ins "::mlir::TypeRange":$resultTypes,
+ "::mlir::StringRef":$moduleName,
+ "::mlir::StringRef":$name,
+ "::circt::firrtl::NameKindEnum":$nameKind,
+ "::mlir::ArrayRef<Direction>":$portDirections,
+ "::mlir::ArrayRef<Attribute>":$portNames,
+ "ArrayRef<Attribute>":$annotations,
+ "ArrayRef<Attribute>":$portAnnotations,
+ "::mlir::ArrayRef<Attribute>":$layers,
+ "bool":$lowerToBind,
+ "hw::InnerSymAttr":$innerSym)>,
+
+ /// Constructor when you have the target module in hand.
+ OpBuilder<(ins "FModuleLike":$module,
+ "mlir::StringRef":$name,
+ CArg<"NameKindEnum", "NameKindEnum::DroppableName">:$nameKind,
+ CArg<"ArrayRef<Attribute>", "{}">:$annotations,
+ CArg<"ArrayRef<Attribute>", "{}">:$portAnnotations,
+ CArg<"bool","false">:$lowerToBind,
+ CArg<"hw::InnerSymAttr", "hw::InnerSymAttr()">:$innerSym)>,
+
+ /// Constructor when you have a port info list in hand.
+ OpBuilder<(ins "ArrayRef<PortInfo>":$ports,
+ "::mlir::StringRef":$moduleName,
+ "mlir::StringRef":$name,
+ CArg<"NameKindEnum", "NameKindEnum::DroppableName">:$nameKind,
+ CArg<"ArrayRef<Attribute>", "{}">:$annotations,
+ CArg<"ArrayRef<Attribute>", "{}">:$layers,
+ CArg<"bool","false">:$lowerToBind,
+ CArg<"hw::InnerSymAttr", "hw::InnerSymAttr()">:$innerSym)>
+ ];
+
+ let extraClassDeclaration = [{
+ /// Return the port direction for the specified result number.
+ Direction getPortDirection(size_t resultNo) {
+ return direction::get(getPortDirections()[resultNo]);
+ }
+
+ /// Return the port name for the specified result number.
+ StringAttr getPortName(size_t resultNo) {
+ return cast<StringAttr>(getPortNames()[resultNo]);
+ }
+ StringRef getPortNameStr(size_t resultNo) {
+ return getPortName(resultNo).getValue();
+ }
+
+ /// Hooks for port annotations.
+ ArrayAttr getPortAnnotation(unsigned portIdx);
+ void setAllPortAnnotations(ArrayRef<Attribute> annotations);
+
+ /// Builds a new `StrictInstanceOp` with the ports listed in `portIndices` erased,
+ /// and updates any users of the remaining ports to point at the new
+ /// instance.
+ StrictInstanceOp erasePorts(OpBuilder &builder, const llvm::BitVector &portIndices);
+
+ /// Clone the instance op and add ports. This is usually used in
+ /// conjuction with adding ports to the referenced module. This will emit
+ /// the new StrictInstanceOp to the same location.
+ StrictInstanceOp cloneAndInsertPorts(ArrayRef<std::pair<unsigned, PortInfo>> ports);
+
+ //===------------------------------------------------------------------===//
+ // Instance graph methods
+ //===------------------------------------------------------------------===//
+
+ // Quick lookup of the referenced module using the instance graph.
+ template <typename T = ::circt::igraph::ModuleOpInterface>
+ T getReferencedModule(::circt::igraph::InstanceGraph &instanceGraph) {
+ auto moduleNameAttr = getModuleNameAttr().getAttr();
+ auto *node = instanceGraph.lookup(moduleNameAttr);
+ if (!node)
+ return nullptr;
+ Operation *moduleOp = node->getModule();
+ return dyn_cast_or_null<T>(moduleOp);
+ }
+ }];
+
+ let hasVerifier = true;
+}
+
 def InstanceChoiceOp : HardwareDeclOp<"instance_choice", [
  DeclareOpInterfaceMethods<SymbolUserOpInterface>
  ]> {
@@ -579,6 +701,41 @@ def RegResetOp : HardwareDeclOp<"regreset", [Forceable, CombDataflow]> {
  let hasVerifier = 1;
 }
 
+def StrictRegOp : HardwareDeclOp<"strictreg", [Forceable, SameVariadicOperandSize]> {
+ let summary = "Define a new register with an optional reset";
+ let description = [{
+ Declare a new register:
+ ```
+ %name, %name_write = firrtl.regreset %clockVal (reset %resetSignal, %resetValue)? : t1 (, rt)?
+ ```
+ }];
+
+ let arguments = (
+ ins ClockType:$clockVal, 
+ Optional<AnyResetType>:$resetSignal,
+ Optional<AnyRegisterType>:$resetValue,
+ StrAttr:$name, NameKindAttr:$nameKind,
+ AnnotationArrayAttr:$annotations,
+ OptionalAttr<InnerSymAttr>:$inner_sym,
+ UnitAttr:$forceable);
+ let results = (outs AnyRegisterType:$read, LHSType:$write, Optional<RefType>:$ref);
+
+ let assemblyFormat = [{
+ (`sym` $inner_sym^)? `` custom<NameKind>($nameKind)
+ $clockVal (`,` `reset` `(` $resetSignal^ `:` type($resetSignal) `,` $resetValue `:` type($resetValue) `)` )? (`,` `forceable` $forceable^)? `` custom<FIRRTLImplicitSSAName>(attr-dict)
+ `:` type($clockVal) `,` custom<OptionalLHSOpTypes>(type($write), type($read)) (`,` qualified(type($ref))^)?
+
+ }];
+
+// let hasCanonicalizer = true;
+// let hasVerifier = 1;
+
+ let extraClassDeclaration = [{
+ Value getResult();
+ }];
+}
+
+
 def WireOp : HardwareDeclOp<"wire", [
  Forceable,
  DeclareOpInterfaceMethods<SymbolUserOpInterface>
@@ -670,6 +827,41 @@ def WireOp : HardwareDeclOp<"wire", [
  }];
 }
 
+def StrictWireOp : HardwareDeclOp<"strictwire", [
+ Forceable,
+ LHSTypeConstraint<"read", "write">,
+ OptRefTypeConstraint<"read", "ref">,
+ DeclareOpInterfaceMethods<SymbolUserOpInterface>
+]> {
+ let summary = "Define a new wire";
+ let description = [{
+ Declare a new wire:
+ ```
+ %name,%name.wp,%name.ref = firrtl.strictwire forceable : t1
+ ```
+ }];
+
+ let arguments = (ins StrAttr:$name, NameKindAttr:$nameKind,
+ AnnotationArrayAttr:$annotations,
+ OptionalAttr<InnerSymAttr>:$inner_sym,
+ UnitAttr:$forceable); // ReferenceKinds
+ let results = (outs PassiveType:$read, 
+ LHSType:$write,
+ Optional<RefType>:$ref);
+
+// let hasCanonicalizer = true;
+
+ let assemblyFormat = [{
+ (`sym` $inner_sym^)? `` custom<NameKind>($nameKind)
+ (`forceable` $forceable^)? `` custom<FIRRTLImplicitSSAName>(attr-dict) `:`
+ custom<OptionalLHSOpTypes>(type($write), type($read)) (`,` qualified(type($ref))^)?
+ }];
+
+ let extraClassDeclaration = [{
+ Value getResult();
+ }];
+}
+
 //===----------------------------------------------------------------------===//
 // Property Ops
 //===----------------------------------------------------------------------===//

include/circt/Dialect/FIRRTL/FIRRTLExpressions.td

@@ -271,7 +271,7 @@ def InvalidValueOp : FIRRTLOp<"invalidvalue",
  let assemblyFormat = "attr-dict `:` qualified(type($result))";
 }
 
-class BaseSubfieldOp<string name, Type btype, Type rtype> : FIRRTLExprOp<name> {
+class BaseSubfieldOp<string name, Type btype, Type itype, Type rtype> : FIRRTLExprOp<name> {
  let summary = "Extract a subfield of another value";
  let description = [{
  The subfield expression refers to a subelement of an expression with a
@@ -281,44 +281,55 @@ class BaseSubfieldOp<string name, Type btype, Type rtype> : FIRRTLExprOp<name> {
  ```
  }];
 
- let arguments = (ins btype:$input, I32Attr:$fieldIndex);
+ let arguments = (ins itype:$input, I32Attr:$fieldIndex);
  let results = (outs rtype:$result);
  let hasVerifier = 1;
  let hasCustomAssemblyFormat = 1;
 
  let builders = [
  OpBuilder<(ins "Value":$input, "StringRef":$fieldName), [{
- auto bundleType = firrtl::type_cast<}] # btype # [{>(input.getType());
+ auto ttype = isa<LHSType>(input.getType()) ? cast<LHSType>(input.getType()).getType() : input.getType();
+ auto bundleType = firrtl::type_cast<}] # btype # [{>(ttype);
  auto fieldIndex = bundleType.getElementIndex(fieldName);
  assert(fieldIndex.has_value() && "subfield operation to unknown field");
  return build($_builder, $_state, input, *fieldIndex);
  }]>
  ];
 
  let firrtlExtraClassDeclaration = [{
- using InputType = }] # btype # [{;
+ using InputType = }] # itype # [{;
+ using InputBundleType = }] # btype # [{;
+
+ FIRRTLType stripLHS(FIRRTLType type) {
+ if (auto t = dyn_cast<LHSType>(type))
+ return t.getType();
+ return type;
+ }
 
  /// Return true if the specified field is flipped.
  bool isFieldFlipped();
 
  /// Return a `FieldRef` to the accessed field.
  FieldRef getAccessedField() {
- return FieldRef(getInput(), firrtl::type_cast<InputType>(getInput().getType())
+ auto innerType = stripLHS(getInput().getType());
+ return FieldRef(getInput(), firrtl::type_cast<InputBundleType>(innerType)
  .getFieldID(getFieldIndex()));
  }
 
  /// Return the name of the accessed field.
  StringRef getFieldName() {
- return firrtl::type_cast<InputType>(getInput().getType()).getElementName(getFieldIndex());
+ auto innerType = stripLHS(getInput().getType());
+ return firrtl::type_cast<InputBundleType>(innerType).getElementName(getFieldIndex());
  }
  }];
 }
 
-def SubfieldOp : BaseSubfieldOp<"subfield", BundleType, FIRRTLBaseType> {
+def SubfieldOp : BaseSubfieldOp<"subfield", BundleType, BundleType, FIRRTLBaseType> {
  let hasFolder = 1;
  let hasCanonicalizer = 1;
 }
-def OpenSubfieldOp : BaseSubfieldOp<"opensubfield", OpenBundleType, FIRRTLType>;
+def OpenSubfieldOp : BaseSubfieldOp<"opensubfield", OpenBundleType, OpenBundleType, FIRRTLType>;
+def LHSSubfieldOp : BaseSubfieldOp<"lhssubfield", BundleType, LHSType, LHSType>;
 
 def SubindexOp : FIRRTLExprOp<"subindex"> {
  let summary = "Extract an element of a vector value";
@@ -377,6 +388,35 @@ def OpenSubindexOp : FIRRTLExprOp<"opensubindex"> {
  }];
 }
 
+def LHSSubindexOp : FIRRTLExprOp<"lhssubindex"> {
+ let summary = "Reference an element of a vector value";
+ let description = [{
+ The subindex expression statically refers, by index, to a subelement
+ of an expression with a vector type. The index must be a non-negative
+ integer and cannot be equal to or exceed the length of the vector it
+ indexes.
+ ```
+ %result = firrtl.lhssubindex %input[index] : lhs<t1>
+ ```
+ }];
+
+ let arguments = (ins LHSType:$input, I32Attr:$index);
+ let results = (outs LHSType:$result);
+
+ let assemblyFormat =
+ "$input `[` $index `]` attr-dict `:` qualified(type($input))";
+
+ let firrtlExtraClassDeclaration = [{
+ /// Return a `FieldRef` to the accessed field.
+ FieldRef getAccessedField() {
+ auto btype = cast<BundleType>(getInput().getType().getType());
+ return FieldRef(getInput(), btype.getFieldID(getIndex()));
+ }
+
+ using InputType = FVectorType;
+ }];
+}
+
 def SubaccessOp : FIRRTLExprOp<"subaccess"> {
  let summary = "Extract a dynamic element of a vector value";
  let description = [{

include/circt/Dialect/FIRRTL/FIRRTLStatements.td

@@ -77,6 +77,27 @@ def MatchingConnectOp : FIRRTLOp<"matchingconnect", [FConnectLike,
  custom<OptionalBinaryOpTypes>(type($dest), type($src))}];
 }
 
+def SameAnonLHSTypeOperands: PredOpTrait<
+ "operands must be structurally equivalent with LHS wrapper",
+ CPred<"areAnonymousLHSandTypeEquivalent(getDest().getType(), getSrc().getType())">>;
+def StrictConnectOp : FIRRTLOp<"strictconnect", [FConnectLike,
+ SameAnonLHSTypeOperands]> {
+ let summary = "Connect two signals";
+ let description = [{
+ Connect two values with strict constraints:
+ ```
+ firrtl.strictconnect %dest, %src : t1
+ firrtl.strictconnect %dest, %src : t1, !firrtl.alias<foo, t1>
+ ```
+ }];
+
+ let arguments = (ins LHSType:$dest,
+ SizedPassiveType:$src);
+ let results = (outs);
+
+ let assemblyFormat = [{$dest `,` $src attr-dict `:` custom<OptionalLHSOpTypes>(type($dest), type($src))}];
+}
+
 def RefDefineOp : FIRRTLOp<"ref.define", [SameTypeOperands, FConnectLike]> {
  let summary = "FIRRTL Define References";
  let description = [{

include/circt/Dialect/FIRRTL/FIRRTLTypes.h

@@ -248,6 +248,7 @@ bool isTypeLarger(FIRRTLBaseType dstType, FIRRTLBaseType srcType);
 /// comparison.
 bool areAnonymousTypesEquivalent(FIRRTLBaseType lhs, FIRRTLBaseType rhs);
 bool areAnonymousTypesEquivalent(mlir::Type lhs, mlir::Type rhs);
+bool areAnonymousLHSandTypeEquivalent(LHSType lhs, FIRRTLBaseType rhs);
 
 mlir::Type getPassiveType(mlir::Type anyBaseFIRRTLType);
 

include/circt/Dialect/FIRRTL/FIRRTLTypes.td

@@ -108,6 +108,16 @@ def RWProbe : FIRRTLDialectType<
 def LHSType : FIRRTLDialectType<CPred<"isa<LHSType>($_self)">,
  "writable type", "::circt::firrtl::LHSType">;
 
+class LHSTypeConstraint<string result, string input>
+ : TypesMatchWith<"Result must be lhs of input type",
+ input, result,
+ "type_cast<LHSType>($_self).getType()">;
+
+class OptRefTypeConstraint<string result, string input>
+ : OptionalTypesMatchWith<"Result must be ref of input type",
+ input, result,
+ "type_cast<RefType>($_self).getType()">;
+
 def ConnectableType : AnyTypeOf<[FIRRTLBaseType, ForeignType]>;
 def MatchingConnectableType : AnyTypeOf<[SizedPassiveType, ForeignType]>;