add ro-based puf v0

info.yaml

@@ -1,21 +1,26 @@
 # Tiny Tapeout project information
 project:
-  title:        ""      # Project title
-  author:       ""      # Your name
-  discord:      ""      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
-  description:  ""      # One line description of what your project does
+  title:        "RO-based Physically Unclonable Function (PUF)"      # Project title
+  author:       "Pablo Aravena"      # Your name
+  discord:      "litneet64"      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
+  description:  "Implementation of a Ring Oscillator-based Physically Unclonable Function (PUF) in Sky130"      # One line description of what your project does
   language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
-  clock_hz:     0       # Clock frequency in Hz (or 0 if not applicable)
+  clock_hz:     10_000_000       # Clock frequency in Hz (or 0 if not applicable)
 
   # How many tiles your design occupies? A single tile is about 167x108 uM.
   tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
 
   # Your top module name must start with "tt_um_". Make it unique by including your github username:
-  top_module:  "tt_um_example"
+  top_module:  "tt_um_litneet64_ro_puf"
 
   # List your project's source files here. Source files must be in ./src and you must list each source file separately, one per line:
-  source_files:        
-    - "project.v"
+  source_files:       
+    - "arbiter.v" 
+    - "counter.v"
+    - "mux_16.v"
+    - "ring_osc.v"
+    - "puf_bit.v"
+    - "tt_um_ro_puf.v"
 
 # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
 pinout:

src/arbiter.v

@@ -0,0 +1,29 @@
+module arbiter (
+    input wire out_1, out_2, clk, rst,
+    output wire resp, finish
+);
+    reg marked_1, marked_2;
+
+    assign win_1 = (out_1 & ~out_2 & ~finish);
+    assign win_2 = (out_2 & ~out_1 & ~finish);
+    assign finish = (marked_1 | marked_2);
+
+    always @ (posedge clk) begin
+        if ((marked_1 == 'x && marked_2 == 'x) || rst) begin
+            marked_1 = 0;
+            marked_2 = 0;
+        end
+
+        if (win_1) begin
+            resp = 1;
+            marked_1 = 1;
+        end
+
+        else if (win_2) begin
+            resp = 0;
+            marked_2 = 1;
+        end
+
+    end
+
+endmodule

src/counter.v

@@ -0,0 +1,27 @@
+module counter(
+    input wire in, clk, rst,
+    output wire out
+);
+    reg[15:0] ctr;
+    reg finish;
+
+    assign threshold = 'b11111111_11111111;
+    assign out = (finish) ? 1 : 0;
+
+    always @ (posedge clk) begin
+        if (in) begin
+            ctr = ctr + 1;
+        end
+
+        if (rst) begin
+            ctr = 0;
+            finish = 0;
+        end
+
+        if (ctr == threshold) begin
+            finish = 1;
+        end
+    end
+
+
+endmodule

src/mux_16.v

@@ -0,0 +1,32 @@
+module mux_16 (
+    input wire[15:0] ro,
+    input wire[3:0] chall,
+    output wire out
+);
+    reg sel;
+    assign out = sel;
+
+    always @ (*) begin
+        case (chall)
+            'd0: sel = ro[0];
+            'd1: sel = ro[1];
+            'd2: sel = ro[2];
+            'd3: sel = ro[3];
+            'd4: sel = ro[4];
+            'd5: sel = ro[5];
+            'd6: sel = ro[6];
+            'd7: sel = ro[7];
+            'd8: sel = ro[8];
+            'd9: sel = ro[9];
+            'd10: sel = ro[10];
+            'd11: sel = ro[11];
+            'd12: sel = ro[12];
+            'd13: sel = ro[13];
+            'd14: sel = ro[14];
+            'd15: sel = ro[15];
+            default: sel = 'bx;
+        endcase
+    end
+
+
+endmodule

src/puf_bit.v

@@ -0,0 +1,29 @@
+module puf_bit(
+    input wire[7:0] chall,
+    input wire clk, rst, en,
+    output wire resp, finish
+);
+
+    localparam n_ro = 32;
+    localparam n_half = n_ro / 2;
+
+    wire[n_ro-1:0] ro_out;
+    reg[n_ro-1:0] inter_en;
+
+    wire mux_out_1, mux_out_2;
+    wire ctr_out_1, ctr_out_2;
+
+    assign inter_en[n_ro-1:0] = n_ro'd1;
+
+    ring_osc ro_array_1[n_half-1:0] (inter_en[n_half-1:0], ro_out[n_half-1:0]);
+    ring_osc ro_array_2[n_half-1:0] (inter_en[n_ro-1:n_half], ro_out[n_ro-1:n_half]);
+
+    mux_16 mux_1(ro_out[n_half-1:0], chall[3:0], mux_out_1);
+    mux_16 mux_2(ro_out[n_ro-1:n_half], chall[7:4], mux_out_2);
+
+    counter cnt_1(mux_out_1, clk, rst, ctr_out_1);
+    counter cnt_2(mux_out_2, clk, rst, ctr_out_2);
+
+    arbiter race_arb(cnt_out_1, cnt_out_2, clk, rst, resp, finish);
+
+endmodule

src/ring_osc.v

@@ -0,0 +1,22 @@
+
+module ring_osc(
+    input wire en,
+    output wire out
+    );
+
+    localparam num_inv = 7;
+    genvar i;
+
+    wire inter_wire[num_inv:0];
+
+    generate
+        for (i = 0; i < num_inv; i = i+1) begin
+            sky130_fd_sc_hd__inv_2 inv(inter_wire[i], inter_wire[i+1]);
+        end
+    endgenerate
+
+    and and_gate(inter_wire[0], out, en);
+    assign out = inter_wire[num_inv];
+
+endmodule 
+

src/project.v → src/tt_um_ro_puf.v

@@ -1,11 +1,9 @@
 /*
- * Copyright (c) 2024 Your Name
+ * Copyright (c) 2024 Pablo Aravena
  * SPDX-License-Identifier: Apache-2.0
  */
 
-`default_nettype none
-
-module tt_um_example (
+module tt_um_litneet64_ro_puf (
     input  wire [7:0] ui_in,    // Dedicated inputs
     output wire [7:0] uo_out,   // Dedicated outputs
     input  wire [7:0] uio_in,   // IOs: Input path
@@ -16,12 +14,25 @@ module tt_um_example (
     input  wire       rst_n     // reset_n - low to reset
 );
 
+  assign rst = ~rst_n;
+
   // All output pins must be assigned. If not used, assign to 0.
-  assign uo_out  = ui_in + uio_in;  // Example: ou_out is the sum of ui_in and uio_in
-  assign uio_out = 0;
-  assign uio_oe  = 0;
+  assign uio_in = 8'b00000000;
+  assign uio_out = 8'b00000000;
+  assign uio_oe  = 8'b00000000;
 
   // List all unused inputs to prevent warnings
-  wire _unused = &{ena, clk, rst_n, 1'b0};
+  //wire _unused = &{1'b0};
+
+  localparam n_bits = 8;
+  wire[n_bits-1:0] finish;
+
+  genvar i;
+
+  generate
+    for (i = 0; i < n_bits; i = i+1) begin
+      puf_bit puf_buffer(ui_in[n_bits-1:0], clk, rst, ena, uo_out[i], finish[i]);
+    end
+  endgenerate
 
 endmodule