fix: change wire int assignment 4

src/puf_bit.v

@@ -9,11 +9,17 @@ module puf_bit(
     localparam n_half = n_ro / 2;
 
     wire[n_ro-1:0] ro_out;
-    reg[n_ro-1:0] inter_en = (en) ? n_ro'b1 : n_ro'b0;
+    reg[n_ro-1:0] inter_en;
 
     wire mux_out_1, mux_out_2;
     wire ctr_out_1, ctr_out_2;
 
+    always @ (posedge clk) begin
+        if (en && inter_en == n_ro'x) begin
+            inter_en <= n_ro'b1;
+        end
+    end
+
     ring_osc ro_array_1[n_half-1:0] (inter_en[n_half-1:0], ro_out[n_half-1:0]);
     ring_osc ro_array_2[n_half-1:0] (inter_en[n_ro-1:n_half], ro_out[n_ro-1:n_half]);