fix: bare bones tests

litneet64 · May 31, 2024 · 5bc6c9d · 5bc6c9d
1 parent e395541
commit 5bc6c9d
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Showing 2 changed files with 2 additions and 2 deletions.
diff --git a/test/Makefile b/test/Makefile
@@ -5,7 +5,7 @@
 SIM ?= icarus
 TOPLEVEL_LANG ?= verilog
 SRC_DIR = $(PWD)/../src
-PROJECT_SOURCES = project.v
+PROJECT_SOURCES = arbiter.v counter.v mux_16.v ring_osc.v puf_bit.v tt_um_ro_puf.v
 
 ifneq ($(GATES),yes)
 

diff --git a/test/tb.v b/test/tb.v
@@ -24,7 +24,7 @@ module tb ();
   wire [7:0] uio_oe;
 
   // Replace tt_um_example with your module name:
-  tt_um_example user_project (
+  tt_um_litneet64_ro_puf user_project (
 
       // Include power ports for the Gate Level test:
 `ifdef GL_TEST