Amaranth 0.5.3 (kuznia-rdzeni/coreblocks#754)

kuznia-rdzeni · Nov 25, 2024 · e3f5a22 · e3f5a22
1 parent 5c44ab8
commit e3f5a22
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Showing 4 changed files with 13 additions and 78 deletions.
diff --git a/test/testing/test_log.py b/test/testing/test_log.py
@@ -95,6 +95,7 @@ def test_error_log(self, caplog):
         async def proc(sim: TestbenchContext):
             await sim.tick()
             sim.set(m.input, 1)
+            await sim.tick()  # A log after the last tick is not handled
 
         with pytest.raises(AssertionError):
             with self.run_simulation(m) as sim:
@@ -112,6 +113,7 @@ def test_assertion(self, caplog):
         async def proc(sim: TestbenchContext):
             await sim.tick()
             sim.set(m.input, 1)
+            await sim.tick()  # A log after the last tick is not handled
 
         with pytest.raises(AssertionError):
             with self.run_simulation(m) as sim:

diff --git a/transactron/testing/gtkw_extension.py b/transactron/testing/gtkw_extension.py
diff --git a/transactron/testing/infrastructure.py b/transactron/testing/infrastructure.py
@@ -16,7 +16,6 @@
 from .profiler import profiler_process, Profile
 from .logging import make_logging_process, parse_logging_level, _LogFormatter
 from .tick_count import make_tick_count_process
-from .gtkw_extension import write_vcd_ext
 from .method_mock import MethodMock
 from transactron import Method
 from transactron.lib import AdapterTrans
@@ -156,22 +155,27 @@ def __init__(
                 extra_signals = extra_signals()
             clocks = [d.clk for d in cast(Any, self)._design.fragment.domains.values()]
 
-            self.ctx = write_vcd_ext(
-                cast(Any, self)._engine,
+            self.ctx = self.write_vcd(
                 f"{traces_dir}/{traces_file}.vcd",
                 f"{traces_dir}/{traces_file}.gtkw",
                 traces=[clocks, extra_signals],
             )
         else:
             self.ctx = nullcontext()
 
-        self.deadline = clk_period * max_cycles
+        self.timeouted = False
+
+        async def timeout_testbench(sim: SimulatorContext):
+            await sim.delay(clk_period * max_cycles)
+            self.timeouted = True
+
+        self.add_testbench(timeout_testbench, background=True)
 
     def run(self) -> bool:
         with self.ctx:
-            self.run_until(self.deadline)
+            super().run()
 
-        return not self.advance()
+        return not self.timeouted
 
 
 class TestCaseWithSimulator:

diff --git a/transactron/testing/logging.py b/transactron/testing/logging.py
@@ -97,7 +97,7 @@ async def log_process(sim: ProcessContext) -> None:
         ticks = DependencyContext.get().get_dependency(TicksKey())
 
         async for _, _, ticks_val, combined_trigger_val, *record_vals in (
-            sim.tick("sync_neg")
+            sim.tick()
             .sample(ticks, combined_trigger)
             .sample(*itertools.chain(*([record.trigger] + record.fields for record in records)))
         ):