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# This module was copied from Amaranth because it is deprecated there. | ||
# Copyright (C) 2019-2024 Amaranth HDL contributors | ||
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from amaranth.hdl import * | ||
from amaranth.sim import * | ||
from transactron.utils.amaranth_ext.coding import * | ||
from transactron.testing import * | ||
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class TestEncoder(TestCaseWithSimulator): | ||
def test_basic(self): | ||
enc = Encoder(4) | ||
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async def process(sim: TestbenchContext): | ||
assert sim.get(enc.n) == 1 | ||
assert sim.get(enc.o) == 0 | ||
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sim.set(enc.i, 0b0001) | ||
assert sim.get(enc.n) == 0 | ||
assert sim.get(enc.o) == 0 | ||
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sim.set(enc.i, 0b0100) | ||
assert sim.get(enc.n) == 0 | ||
assert sim.get(enc.o) == 2 | ||
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sim.set(enc.i, 0b0110) | ||
assert sim.get(enc.n) == 1 | ||
assert sim.get(enc.o) == 0 | ||
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with self.run_simulation(enc) as sim: | ||
sim.add_testbench(process) | ||
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class TestPriorityEncoder(TestCaseWithSimulator): | ||
def test_basic(self): | ||
enc = PriorityEncoder(4) | ||
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async def process(sim: TestbenchContext): | ||
assert sim.get(enc.n) == 1 | ||
assert sim.get(enc.o) == 0 | ||
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sim.set(enc.i, 0b0001) | ||
assert sim.get(enc.n) == 0 | ||
assert sim.get(enc.o) == 0 | ||
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sim.set(enc.i, 0b0100) | ||
assert sim.get(enc.n) == 0 | ||
assert sim.get(enc.o) == 2 | ||
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sim.set(enc.i, 0b0110) | ||
assert sim.get(enc.n) == 0 | ||
assert sim.get(enc.o) == 1 | ||
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sim.set(enc.i, 0b1110) | ||
assert sim.get(enc.n) == 0 | ||
assert sim.get(enc.o) == 1 | ||
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with self.run_simulation(enc) as sim: | ||
sim.add_testbench(process) | ||
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class TestDecoder(TestCaseWithSimulator): | ||
def test_basic(self): | ||
dec = Decoder(4) | ||
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async def process(sim: TestbenchContext): | ||
assert sim.get(dec.o) == 0b0001 | ||
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sim.set(dec.i, 1) | ||
assert sim.get(dec.o) == 0b0010 | ||
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sim.set(dec.i, 3) | ||
assert sim.get(dec.o) == 0b1000 | ||
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sim.set(dec.n, 1) | ||
assert sim.get(dec.o) == 0b0000 | ||
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with self.run_simulation(dec) as sim: | ||
sim.add_testbench(process) |
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