Merge branch 'master' into coreblocks

.github/workflows/ci.yml

@@ -38,7 +38,7 @@ jobs:
       # Install (n)Migen / LiteX / Cores
       - name: Install LiteX
         run: |
-          python3 litex_setup.py --config=full --init --install --user
+          python3 litex_setup.py --config=full --init --install --user --dev
 
       # Install GCC Toolchains
       - name: Install GCC Toolchains
@@ -54,6 +54,7 @@ jobs:
           export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
           git clone https://github.com/verilator/verilator
           cd verilator
+          git checkout 7d2d32420a630befa4097170ecbf227e04e32522
           autoconf
           ./configure
           make -j$(nproc)

CHANGES.md

@@ -1,5 +1,152 @@
-[> Changes since 2022.12
+[> Changes since 2023.12
 ------------------------
+	[> Fixed
+	--------
+	- integration/soc               : Fixed typo in cpu mem_bus axi-via-wb downconvert
+	- interconnect/ahb/AHB2Wishbone : Fixed size check that was too restrictive.
+	- liteeth/phy/gw5rgmii          : Fixed Clk assignments.
+	- build/efinix/programmer       : Updated for compatibility with latest Efinity versions.
+	- litespi/software:             : Fixed SPI Flash Clk Divider computation when with L2 Cache.
+
+	[> Added
+	--------
+	- build/openfpgaloader          : Added kwargs support to flash for specific/less common cases.
+	- cpu/gowin_emcu                : Improved/Cleaned-up.
+	- interconnect/ahb              : Added data_width/address_width parameters.
+	- interconnect/ahb              : Added proper byte/sel support to AHB2Wishbone.
+	- cpu/gowin_ae350               : Added initial support.
+	- cpu/naxriscv                  : Updated arch definition and added rvc configuration parameters.
+	- cpu/vexriscv_smp              : Added csr/clint/plic base address configuration parameters.
+	- liteeth/phy                   : Added 7-Series/Ultrascale(+) 2500BaseX PHYs.
+	- litespi/sdrphy:               : Allowed flash parameter to be None.
+	- litespi/integration           : Improved integration and simplifications.
+
+	[> Changed
+	----------
+
+[> 2023.12, released on December 25th 2023
+------------------------------------------
+	[> Fixed
+	--------
+	- liteeth/arp           : Fixed response on table update.
+	- litesata/us(p)sataphy : Fixed data_width=32 case.
+	- clock/lattice_ecp5    : Fixed phase calculation.
+	- interconnect/axi      : Fixed AXILite2CSR read access (1 CSR cycle instead of 2).
+
+	[> Added
+	--------
+	- cpu/naxriscv          : Added SMP support.
+	- cpu/neorv32           : Added Debug support and update core complex.
+	- cpu/vexriscv_smp      : Added hardware breakpoints support.
+	- build/colognechip     : Added initial support.
+	- soc/cores/video       : Added VTG/DMA synchronization stage to VideoFramebuffer.
+	- litepcie/dma          : Improved LitePCIeDMADescriptorSplitter timings.
+	- interconnect/wishbone : Added linear burst support to DownConverter.
+	- integration/SoC       : Added with_jtagbone/with_uartbone support.
+	- soc/cores             : Added Ti60F100 HyperRAM support.
+	- build/xilinx          : Added initial OpenXC7 support (and improved Yosys-NextPnr).
+	- build/efinix          : Added JTAG-UART/JTAGBone support.
+	- interconnect/wishbone : Added byte/word addressing support.
+	- cores/uart            : Added 64-bit addressing support to Stream2Wishbone.
+	- tools                 : Added 64-bit addressing support to litex_server/client.
+	- cores/cpu             : Added 64-bit support to CPUNone.
+	- cores/cpu             : Added KianV (RV32IMA) initial support.
+	- litedram              : Added initial GW5DDRPHY (compiles but not yet working).
+	- build/gowin           : Added GowinTristate implementation.
+	- litepcie              : Simplify/Cleanup Ultrascale(+) integration and allow .xci generation from .tcl.
+	- litepcie              : Initial 64-bit DMA suppport.
+	- bios                  : Added bios_format / --bios-format to allow enabling float/double printf.
+	- soc/cores/clock       : Added proper clock feedback support on Efinix TRIONPLL/TITANIUMPLL.
+	- liteiclink/phy        : Added Efinix support/examples on Trion/Titanium.
+	- liteiclink/serwb      : Reused Etherbone from LiteEth to avoid code duplication.
+	- interconnect          : Added 64-bit support to Wishbone/AXI-Lite/AXI.
+	- jtag                  : Fixed firmware upload over JTAG-UART.
+	- jtag                  : Improved speed (~X16) on JTABone/JTAGUART on all supported devices (Xilinx, Altera, Efinix, etc...)
+	- litesata/phy          : Added GTHE4 support on Ultrascale+.
+	- litex_boards          : Added Machdyne's Mozart with the Sechzig ML1 module support.
+	- liteiclink            : Added clk_ratio of 1:2, 1:4 on Efinix/SerWB to make clocking more flexible.
+
+	[> Changed
+	----------
+	- build/osfpga          : Removed initial support (would need feedbacks/updates).
+	- python3               : Updated minimum python3 version to 3.7 (To allow more than 255 arguments in functions).
+
+[> 2023.08, released on September 14th 2023
+-------------------------------------------
+
+	[> Fixed
+	--------
+	- lattice/programmer  : Fixed ECPDAP frequency specification.
+	- soc/add_spi_sdcard  : Fixed Tristate build.
+	- csr/fields          : Fixed access type checks.
+	- software/liblitespi : Fixed support with debug.
+	- cpu/vexriscv_smp    : Fixed compilation with Gowin toolchain (ex for Tang Nano 20K Linux).
+	- liteiclink/serwb    : Fixed 7-Series initialization corner cases.
+	- liteeth/core/icmp   : Fixed length check on LiteEthICMPEcho before passing data to buffer.
+	- LiteXModule/CSR     : Fixed CSR collection order causing CSR clock domain to be changed.
+	- litepcie/US(P)      : Fixed root cause of possible MSI deadlock.
+	- soc/add_uart        : Fixed stub behavior (sink/source swap).
+	- build/efinix        : Fixed AsyncFIFO issues (Minimum of 2 buffer stages).
+	- software/gcc        : Fixed Ubuntu 22.04 GCC compilation issues.
+	- build/efinix        : Fixed hardcoded version.
+	- litedram/gw2ddrphy  : Fixed latencies and tested on Tang Primer 20K.
+
+	[> Added
+	--------
+	- soc/cores/video              : Added low resolution video modes.
+	- interconnect                 : Added initial AvalonMM support.
+	- soc/interconnect/packet      : Avoided bypass of dispatcher with a single slave.
+	- build/add_period_constraints : Improved generic platform and simplify specific platforms.
+	- gen/fhdl/verilog             : Added parameter to avoid register initialization (required for ASIC).
+	- litedram                     : Added clamshell topology support.
+	- stream/Pipeline              : Added dynamic pipeline creation capability.
+	- build/xilinx/vivado          : Added project commands to allow adding commands just after project creation.
+	- soc/software                 : Moved helpers to hw/common.h.
+	- tools/litex_json2dts_linux   : Added sys_clk to device tree and fixed dts warning.
+	- tools/litex_json2dts_zephyr  : Added LiteSD defines.
+	- build/yosys                  : Added quiet capability.
+	- build/efinix                 : Improved Titanium support (PLL, DRIVE_STRENGTH, SLEW).
+	- build/openfpgaloader         : Added -fpga-part and -index-chain support.
+	- soc/add_spi_flash            : Added software_debug support.
+	- software/liblitespi          : Added read_id support.
+	- litex_boards                 : Added QMtech XC7K325T, VCU128, SITLINV_STVL7325_V2, Enclustra XU8/PE3 support.
+	- liteeth                      : Added Ultrascale+ GTY/GTH SGMII/1000BaseX PHYs.
+	- soc/add_pcie                 : Added msi_type parameter to select MSI, MSI-Multi-Vector or MSI-X.
+	- soc/add_pcie                 : Added msi_width parameter to select MSI width.
+	- litepcie                     : Added 7-Series MSI-X capability/integration.
+	- liteiclink                   : Improved GTH3/GTH4 support and similarity with Wizard's generated code.
+	- liteeth_gen                  : Added SGMII/1000BaseX PHYs support.
+	- litesata/dma                 : Added multi-sector support.
+	- liteeth/mac                  : Added TX Slots write-only mode for improved resource usage when software does not read buffer.
+	- liteeth/core                 : Added DHCP support for CPU-less hardware stack.
+	- liteeth/core/icmp            : Added fifo_depth parameter on LiteEthICMPEcho.
+	- gen/fhdl/verilog             : Improved signal sort by name instead of duid to improve reproducibility.
+	- litedram/frontend/dma        : Added last generation on end of DMA for LiteDRAMDMAReader.
+	- litepcie/frontend/dma        : Added optional integrated data-width converter and data_width parameters to simplify integration/user logic.
+	- soc/add_uartbone/sata/sdcard : Added support for multiple instances in gateware as for the other cores.
+	- liteeth_gen                  : Added raw UDP port support.
+	- build/vivado                 : Added .dcp generation also after synthesis and placement.
+	- gen:                         : Added initial LiteXContext to easily get build properties (platform, device, toolchain, etc...)
+	- litepcie/endpoint/tlp        : Added optional Configuration/PTM TLP support to Packetizer/Depacketizer.
+	- liteth/arp                   : Added proper multi-entries ARP table.
+	- liteiclink/serdes            : Added tx/rx_clk sharing capabilities on Xilinx transceivers.
+	- soc/cores/spi                : Added new SPIMMAP core allowing SPI accesses through MMAP.
+	- soc/interconnect/stream      : Added pipe_valid/pipe_ready parameters to BufferizeEndpoints.
+	- soc/cores/clock              : Added initial GW5A support.
+	- build/efinix                 : Added initial EfinixDDROutput/Input and simplified IOs exclusion.
+	- soc/interconnect             : Improved DMA Bus to use the same Bus Standard than the CPU DMA Bus.
+	- liteeth/phy                  : Added Artix7 2500BASE-X PHY.
+	- liteeth/phy                  : Added Gowin Arora V RGMII PHY (GW5RGMII).
+	- liteeth/phy                  : Added Titanium RGMII PHY (Tested with Ti60 F225 + RGMII adapter board).
+	- build/io                     : Added ClkInput/Ouput IO abstraction to simplify some Efinix designs.
+
+	[> Changed
+	----------
+	- litex/gen                    : Added local version of genlib.cdc/misc to better decouple with Migen and prepare Amaranth's compat use.
+	- soc/add_uartbone             : Renamed name parameter to uart_name (for consistency with other cores).
+
+[> 2023.04, released on May 8th 2023
+------------------------------------
 
 	[> Fixed
 	--------
@@ -18,6 +165,8 @@
 	- cpu/soc             : Fixed CPU IRQ reservation.
 	- litepcie/software   : Fixed compilation with DMA_CHECK_DATA commented.
 	- litedram/dma        : Fixed rdata connection (omit list update since LiteX AXI changes).
+	- litepcie/US(P)      : Fixed possible MSI deadlock.
+	- cores/usb_ohci      : Fixed build issue (usb_clk_freq wrapped as int).
 
 	[> Added
 	--------
@@ -80,6 +229,8 @@
 	- litedram/bist       : Replicated data for large data-width.
 	- litedram/ci         : Allowed tests to run in parallel.
 	- litedram/gw2ddrphy  : Improvements to remove warnings in simulation.
+	- liblitespi/spiflash : Add erasee and write functions.
+	- liblitespi/Spiflash : Add write from sdcard file function.
 
 	[> Changed
 	----------