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Delay flush by one cycle #762

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Delay flush by one cycle #762

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1e4936c
Delay flush by one cycle
tilk Nov 26, 2024
32b3beb
Remove core_flushing signal
tilk Nov 26, 2024
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18 changes: 4 additions & 14 deletions coreblocks/backend/retirement.py
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,6 @@
from coreblocks.interface.layouts import RetirementLayouts

from transactron.core import Method, Transaction, TModule, def_method
from transactron.lib.simultaneous import condition
from transactron.utils.dependencies import DependencyContext
from transactron.lib.metrics import *

Expand Down Expand Up @@ -115,7 +114,6 @@ def flush_instr(rob_entry):

continue_pc_override = Signal()
continue_pc = Signal(self.gen_params.isa.xlen)
core_flushing = Signal()

with m.FSM("NORMAL") as fsm:
with m.State("NORMAL"):
Expand Down Expand Up @@ -180,15 +178,8 @@ def flush_instr(rob_entry):
# Normally retire all non-trap instructions
m.d.av_comb += commit.eq(1)

# Condition is used to avoid FRAT locking during normal operation
with condition(m) as cond:
with cond(commit):
retire_instr(rob_entry)
with cond():
# Not using default condition, because we want to block if branch is not ready
flush_instr(rob_entry)

m.d.comb += core_flushing.eq(1)
with m.If(commit):
retire_instr(rob_entry)
Comment on lines -183 to +182
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This is not valid - when instruction is an exception with commit=0 (like synchronous exceptions),
RF is not freed (and not pushed to Free RF), but instruction is retired from ROB, and TRAP_FLUSH would flush next instruction.

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Indeed, you're right - this was not thought out enough. Still, this means we have a blind spot in tests for this.


validate_transaction.schedule_before(retire_transaction)

Expand All @@ -205,8 +196,6 @@ def flush_instr(rob_entry):
with m.If(core_empty):
m.next = "TRAP_RESUME"

m.d.comb += core_flushing.eq(1)

with m.State("TRAP_RESUME"):
with Transaction().body(m):
# Resume core operation
Expand All @@ -227,7 +216,8 @@ def flush_instr(rob_entry):
m.next = "NORMAL"

# Disable executing any side effects from instructions in core when it is flushed
m.d.comb += side_fx.eq(~fsm.ongoing("TRAP_FLUSH"))
core_flushing = fsm.ongoing("TRAP_FLUSH")
m.d.comb += side_fx.eq(~core_flushing)

@def_method(m, self.core_state)
def _():
Expand Down