Remove riscvmodel dependency

coreblocks/params/instr.py

@@ -3,7 +3,7 @@
 from amaranth.hdl import ValueCastable
 from amaranth import *
 
-from transactron.utils import ValueLike
+from transactron.utils import ValueLike, int_to_signed
 from coreblocks.params.isa_params import *
 from coreblocks.frontend.decoder.isa import *
 
@@ -53,6 +53,10 @@ def __init__(
     def pack(self) -> Value:
         return Cat(C(0b11, 2), self.opcode, self.rd, self.funct3, self.rs1, self.rs2, self.funct7)
 
+    @staticmethod
+    def encode(opcode: int, rd: int, funct3: int, rs1: int, rs2: int, funct7: int):
+        return int(f"{funct7:07b}{rs2:05b}{rs1:05b}{funct3:03b}{rd:05b}{opcode:05b}11", 2)
+
 
 class ITypeInstr(RISCVInstr):
     def __init__(self, opcode: ValueLike, rd: ValueLike, funct3: ValueLike, rs1: ValueLike, imm: ValueLike):
@@ -65,6 +69,11 @@ def __init__(self, opcode: ValueLike, rd: ValueLike, funct3: ValueLike, rs1: Val
     def pack(self) -> Value:
         return Cat(C(0b11, 2), self.opcode, self.rd, self.funct3, self.rs1, self.imm)
 
+    @staticmethod
+    def encode(opcode: int, rd: int, funct3: int, rs1: int, imm: int):
+        imm = int_to_signed(imm, 12)
+        return int(f"{imm:012b}{rs1:05b}{funct3:03b}{rd:05b}{opcode:05b}11", 2)
+
 
 class STypeInstr(RISCVInstr):
     def __init__(self, opcode: ValueLike, imm: ValueLike, funct3: ValueLike, rs1: ValueLike, rs2: ValueLike):
@@ -77,6 +86,12 @@ def __init__(self, opcode: ValueLike, imm: ValueLike, funct3: ValueLike, rs1: Va
     def pack(self) -> Value:
         return Cat(C(0b11, 2), self.opcode, self.imm[0:5], self.funct3, self.rs1, self.rs2, self.imm[5:12])
 
+    @staticmethod
+    def encode(opcode: int, imm: int, funct3: int, rs1: int, rs2: int):
+        imm = int_to_signed(imm, 12)
+        imm_str = f"{imm:012b}"
+        return int(f"{imm_str[5:12]:07b}{rs2:05b}{rs1:05b}{funct3:03b}{imm_str[0:5]:05b}{opcode:05b}11", 2)
+
 
 class BTypeInstr(RISCVInstr):
     def __init__(self, opcode: ValueLike, imm: ValueLike, funct3: ValueLike, rs1: ValueLike, rs2: ValueLike):
@@ -99,6 +114,16 @@ def pack(self) -> Value:
             self.imm[12],
         )
 
+    @staticmethod
+    def encode(opcode: int, imm: int, funct3: int, rs1: int, rs2: int):
+        imm = int_to_signed(imm, 13)
+        imm_str = f"{imm:013b}"
+        return int(
+            f"{imm_str[12]:01b}{imm_str[5:11]:06b}{rs2:05b}{rs1:05b}{funct3:03b}{imm_str[1:5]:04b}"
+            + f"{imm_str[11]:01b}{opcode:05b}11",
+            2,
+        )
+
 
 class UTypeInstr(RISCVInstr):
     def __init__(self, opcode: ValueLike, rd: ValueLike, imm: ValueLike):
@@ -109,6 +134,11 @@ def __init__(self, opcode: ValueLike, rd: ValueLike, imm: ValueLike):
     def pack(self) -> Value:
         return Cat(C(0b11, 2), self.opcode, self.rd, self.imm[12:])
 
+    @staticmethod
+    def encode(opcode: int, rd: int, imm: int):
+        imm = int_to_signed(imm, 20)
+        return int(f"{imm:020b}{rd:05b}{opcode:05b}11", 2)
+
 
 class JTypeInstr(RISCVInstr):
     def __init__(self, opcode: ValueLike, rd: ValueLike, imm: ValueLike):
@@ -119,6 +149,14 @@ def __init__(self, opcode: ValueLike, rd: ValueLike, imm: ValueLike):
     def pack(self) -> Value:
         return Cat(C(0b11, 2), self.opcode, self.rd, self.imm[12:20], self.imm[11], self.imm[1:11], self.imm[20])
 
+    @staticmethod
+    def encode(opcode: int, rd: int, imm: int):
+        imm = int_to_signed(imm, 21)
+        imm_str = f"{imm:021b}"
+        return int(
+            f"{imm_str[20]:01b}{imm_str[1:11]:010b}{imm_str[11]:01b}{imm_str[12:20]:08b}{rd:05b}{opcode:05b}11", 2
+        )
+
 
 class IllegalInstr(RISCVInstr):
     def __init__(self):
@@ -127,6 +165,10 @@ def __init__(self):
     def pack(self) -> Value:
         return C(1).replicate(32)  # Instructions with all bits set to 1 are reserved to be illegal.
 
+    @staticmethod
+    def encode(opcode: int, rd: int, imm: int):
+        return int("1" * 32, 2)
+
 
 class EBreakInstr(ITypeInstr):
     def __init__(self):

requirements-dev.txt

@@ -3,7 +3,6 @@ black==23.3.0
 docutils==0.15.2
 flake8==6.0.0
 pep8-naming==0.13.3
-git+https://github.com/kristopher38/riscv-python-model@b5d0737#riscv-model
 markupsafe==2.0.1
 myst-parser==0.18.0
 numpydoc==1.5.0

test/test_core.py

@@ -7,7 +7,9 @@
 from transactron.testing import TestCaseWithSimulator, TestbenchIO
 
 from coreblocks.core import Core
+from coreblocks.frontend.decoder import Opcode, Funct3
 from coreblocks.params import GenParams
+from coreblocks.params.instr import *
 from coreblocks.params.configurations import CoreConfiguration, basic_core_config, full_core_config
 from coreblocks.peripherals.wishbone import WishboneSignature, WishboneMemorySlave
 
@@ -16,10 +18,6 @@
 import subprocess
 import tempfile
 from parameterized import parameterized_class
-from riscvmodel.insn import (
-    InstructionADDI,
-    InstructionLUI,
-)
 
 
 class CoreTestElaboratable(Elaboratable):
@@ -81,8 +79,8 @@ def push_register_load_imm(self, reg_id, val):
         if val & 0x800:
             lui_imm = (lui_imm + 1) & (0xFFFFF)
 
-        yield from self.push_instr(InstructionLUI(reg_id, lui_imm).encode())
-        yield from self.push_instr(InstructionADDI(reg_id, reg_id, addi_imm).encode())
+        yield from self.push_instr(UTypeInstr.encode(Opcode.LUI, reg_id, lui_imm))
+        yield from self.push_instr(ITypeInstr.encode(Opcode.OP_IMM, reg_id, Funct3.ADD, reg_id, addi_imm))
 
 
 class TestCoreAsmSourceBase(TestCoreBase):