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Fix profiles on newer yosys version #607

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Mar 12, 2024
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7 changes: 3 additions & 4 deletions test/regression/cocotb.py
Original file line number Diff line number Diff line change
Expand Up @@ -157,10 +157,9 @@ def get_cocotb_handle(self, path_components: list[str]) -> ModifiableObject:
# function instead of 'getattr' - this is required by cocotb.
obj = obj._id(component, extended=False)
except AttributeError:
if component[0] == "\\" and component[-1] == " ":
# workaround for cocotb/verilator weirdness
# for some escaped names lookup fails, but works when unescaped
obj = obj._id(component[1:-1], extended=False)
# Try with escaped name
if component[0] != "\\" and component[-1] != " ":
obj = obj._id("\\" + component + " ", extended=False)
else:
raise

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7 changes: 2 additions & 5 deletions transactron/utils/gen.py
Original file line number Diff line number Diff line change
Expand Up @@ -149,7 +149,7 @@ def escape_verilog_identifier(identifier: str) -> str:
# The standard says how to escape a identifier, but not when. So this is
# a non-exhaustive list of characters that Yosys escapes (it is used
# by Amaranth when generating Verilog code).
characters_to_escape = [".", "$"]
characters_to_escape = [".", "$", "-"]

for char in characters_to_escape:
if char in identifier:
Expand All @@ -160,10 +160,7 @@ def escape_verilog_identifier(identifier: str) -> str:

def get_signal_location(signal: Signal, name_map: "SignalDict") -> list[str]:
raw_location = name_map[signal]

# Amaranth escapes identifiers when generating Verilog code, but returns non-escaped identifiers
# in the name map, so we need to escape it manually.
return [escape_verilog_identifier(component) for component in raw_location]
return raw_location


def collect_metric_locations(name_map: "SignalDict") -> dict[str, MetricLocation]:
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