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Create DependencyManager for gen_verilog.py, regression tests and synthesis #584

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merged 3 commits into from
Feb 12, 2024
Merged

Create DependencyManager for gen_verilog.py, regression tests and synthesis #584

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2e60114
Create DependencyManager for gen_verilog.py and regression tests
Feb 11, 2024
2319b0c
Simplify code
Feb 11, 2024
9c0dbb5
Merge branch 'master' into dep_manager
tilk Feb 12, 2024
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12 changes: 7 additions & 5 deletions scripts/gen_verilog.py
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Original file line number Diff line number Diff line change
Expand Up @@ -17,6 +17,7 @@
from coreblocks.core import Core
from transactron import TransactionModule
from transactron.utils import flatten_signals
from transactron.utils.dependencies import DependencyManager, DependencyContext

from coreblocks.params.configurations import *

Expand All @@ -36,20 +37,21 @@ def __init__(self, gen_params):

def elaborate(self, platform: Platform):
m = Module()
tm = TransactionModule(m)
tm = TransactionModule(m, dependency_manager=DependencyContext.get())

m.submodules.c = Core(gen_params=self.gp, wb_instr_bus=self.wb_instr, wb_data_bus=self.wb_data)

return tm


def gen_verilog(core_config: CoreConfiguration, output_path):
top = Top(GenParams(core_config))
with DependencyContext(DependencyManager()):
top = Top(GenParams(core_config))

with open(output_path, "w") as f:
signals = list(flatten_signals(top.wb_instr)) + list(flatten_signals(top.wb_data))
with open(output_path, "w") as f:
signals = list(flatten_signals(top.wb_instr)) + list(flatten_signals(top.wb_data))

f.write(verilog.convert(top, ports=signals, strip_internal_attrs=True))
f.write(verilog.convert(top, ports=signals, strip_internal_attrs=True))


def main():
Expand Down
12 changes: 7 additions & 5 deletions scripts/synthesize.py
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Expand Up @@ -13,6 +13,7 @@
sys.path.insert(0, parent)


from transactron.utils.dependencies import DependencyContext, DependencyManager
from transactron.utils import ModuleConnector
from coreblocks.params.genparams import GenParams
from coreblocks.params.fu_params import FunctionalComponentParams
Expand Down Expand Up @@ -117,7 +118,7 @@ def unit(gen_params: GenParams):

module = ModuleConnector(fu=fu, issue_connector=issue_connector, accept_connector=accept_connector)

return resources, TransactionModule(module)
return resources, TransactionModule(module, dependency_manager=DependencyContext.get())

return unit

Expand All @@ -138,11 +139,12 @@ def unit(gen_params: GenParams):


def synthesize(core_config: CoreConfiguration, platform: str, core: UnitCore):
gen_params = GenParams(core_config)
resource_builder, module = core(gen_params)
with DependencyContext(DependencyManager()):
gen_params = GenParams(core_config)
resource_builder, module = core(gen_params)

if platform == "ecp5":
make_ecp5_platform(resource_builder)().build(module)
if platform == "ecp5":
make_ecp5_platform(resource_builder)().build(module)


def main():
Expand Down
36 changes: 18 additions & 18 deletions test/regression/pysim.py
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Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,8 @@
from .memory import *
from .common import SimulationBackend, SimulationExecutionResult

from transactron.testing import SimpleTestCircuit, PysimSimulator
from transactron.testing import PysimSimulator
from transactron.utils.dependencies import DependencyContext, DependencyManager
from ..peripherals.test_wishbone import WishboneInterfaceWrapper

from coreblocks.core import Core
Expand Down Expand Up @@ -90,28 +91,27 @@ def f():
return f

async def run(self, mem_model: CoreMemoryModel, timeout_cycles: int = 5000) -> SimulationExecutionResult:
wb_instr_bus = WishboneBus(self.gp.wb_params)
wb_data_bus = WishboneBus(self.gp.wb_params)
core = Core(gen_params=self.gp, wb_instr_bus=wb_instr_bus, wb_data_bus=wb_data_bus)
with DependencyContext(DependencyManager()):
wb_instr_bus = WishboneBus(self.gp.wb_params)
wb_data_bus = WishboneBus(self.gp.wb_params)
core = Core(gen_params=self.gp, wb_instr_bus=wb_instr_bus, wb_data_bus=wb_data_bus)

m = SimpleTestCircuit(core)
wb_instr_ctrl = WishboneInterfaceWrapper(wb_instr_bus)
wb_data_ctrl = WishboneInterfaceWrapper(wb_data_bus)

wb_instr_ctrl = WishboneInterfaceWrapper(wb_instr_bus)
wb_data_ctrl = WishboneInterfaceWrapper(wb_data_bus)
self.running = True
self.cycle_cnt = 0

self.running = True
self.cycle_cnt = 0

sim = PysimSimulator(m, max_cycles=timeout_cycles, traces_file=self.traces_file)
sim.add_sync_process(self._wishbone_slave(mem_model, wb_instr_ctrl, is_instr_bus=True))
sim.add_sync_process(self._wishbone_slave(mem_model, wb_data_ctrl, is_instr_bus=False))
sim.add_sync_process(self._waiter())
success = sim.run()
sim = PysimSimulator(core, max_cycles=timeout_cycles, traces_file=self.traces_file)
sim.add_sync_process(self._wishbone_slave(mem_model, wb_instr_ctrl, is_instr_bus=True))
sim.add_sync_process(self._wishbone_slave(mem_model, wb_data_ctrl, is_instr_bus=False))
sim.add_sync_process(self._waiter())
success = sim.run()

if self.verbose:
print(f"Simulation finished in {self.cycle_cnt} cycles")
if self.verbose:
print(f"Simulation finished in {self.cycle_cnt} cycles")

return SimulationExecutionResult(success)
return SimulationExecutionResult(success)

def stop(self):
self.running = False
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