Faster Wishbone #505
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Faster Wishbone #505
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lekcyjna123
reviewed
Nov 11, 2023
test/peripherals/test_wishbone.py
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| @@ -325,6 +352,7 @@ def mem_op_process(): | |||
| yield from self.m.request.call(addr=addr, data=data, we=write, sel=sel) | |||
| res = yield from self.m.result.call() | |||
| if write: | |||
| yield # workaround, memory state will change the next cycle! | |||
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But this cause that we don't test if request in the first cycle after write works properly.
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The behavior of the request itself is already tested in TestWishboneMaster.
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Updated the test to allow writes without delays, also added random latencies.
piotro888
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Nov 12, 2023
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Apart from @lekcyjna123 comment for TestWishboneMemorySlave, looks good to me
tilk
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Nov 13, 2023
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There was an issue in receiving results from the Wishbone master: if there was latency at receive, requests could disappear. Fixed. |
lekcyjna123
approved these changes
Nov 13, 2023
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This PR improves the performance of the Wishbone master. It's now possible to achieve full utilization of the Wishbone bus: 2 cycles per read and 1 cycle per (unregistered) write. IPC in benchmarks is improved by 12% without Fmax loss.
Truly,
Forwarderis a magic component.