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Fix memory protection in regression tests #481

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merged 5 commits into from
Oct 23, 2023
Merged

Fix memory protection in regression tests #481

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f30a72f
Fix memory segments setting
piotro888 Oct 21, 2023
afc4023
Fix data memory region
piotro888 Oct 22, 2023
a4df4c9
Manually exclude write protection for tests with writeable .text section
piotro888 Oct 22, 2023
587e700
Merge branch 'master' into mem-segments-fix
tilk Oct 23, 2023
b0536e4
Merge branch 'master' into mem-segments-fix
tilk Oct 23, 2023
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2 changes: 1 addition & 1 deletion test/regression/cocotb.py
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Original file line number Diff line number Diff line change
Expand Up @@ -147,7 +147,7 @@ async def run(self, mem_model: CoreMemoryModel, timeout_cycles: int = 5000) -> b
instr_wb = WishboneSlave(self.dut, "wb_instr", self.dut.clk, mem_model, is_instr_bus=True)
cocotb.start_soon(instr_wb.start())

data_wb = WishboneSlave(self.dut, "wb_data", self.dut.clk, mem_model, is_instr_bus=True)
data_wb = WishboneSlave(self.dut, "wb_data", self.dut.clk, mem_model, is_instr_bus=False)
cocotb.start_soon(data_wb.start())

res = await with_timeout(self.finish_event.wait(), timeout_cycles, "ns")
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8 changes: 4 additions & 4 deletions test/regression/memory.py
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Expand Up @@ -137,7 +137,7 @@ def write(self, req: WriteRequest) -> WriteReply:
return WriteReply(status=ReplyStatus.ERROR)


def load_segments_from_elf(file_path: str) -> list[RandomAccessMemory]:
def load_segments_from_elf(file_path: str, *, disable_write_protection: bool = False) -> list[RandomAccessMemory]:
segments: list[RandomAccessMemory] = []

with open(file_path, "rb") as f:
Expand All @@ -160,11 +160,11 @@ def align_down(n: int) -> int:
data = b"\x00" * (paddr - seg_start) + segment.data() + b"\x00" * (seg_end - (paddr + len(segment.data())))

flags = SegmentFlags(0)
if flags_raw & P_FLAGS.PF_R == flags_raw & P_FLAGS.PF_R:
if flags_raw & P_FLAGS.PF_R:
flags |= SegmentFlags.READ
if flags_raw & P_FLAGS.PF_W == flags_raw & P_FLAGS.PF_W:
if flags_raw & P_FLAGS.PF_W or disable_write_protection:
flags |= SegmentFlags.WRITE
if flags_raw & P_FLAGS.PF_X == flags_raw & P_FLAGS.PF_X:
if flags_raw & P_FLAGS.PF_X:
flags |= SegmentFlags.EXECUTABLE

segments.append(RandomAccessMemory(range(seg_start, seg_end), flags, data))
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8 changes: 7 additions & 1 deletion test/regression/test.py
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Expand Up @@ -7,6 +7,9 @@
test_dir = Path(__file__).parent.parent
riscv_tests_dir = test_dir.joinpath("external/riscv-tests")

# disable write protection for specific tests with writes to .text section
exclude_write_protection = ["rv32uc-rvc"]


class MMIO(MemorySegment):
def __init__(self, on_finish: Callable[[], None]):
Expand All @@ -31,7 +34,10 @@ async def run_test(sim_backend: SimulationBackend, test_name: str):
mmio = MMIO(lambda: sim_backend.stop())

mem_segments: list[MemorySegment] = []
mem_segments += load_segments_from_elf(str(riscv_tests_dir.joinpath("test-" + test_name)))
mem_segments += load_segments_from_elf(
str(riscv_tests_dir.joinpath("test-" + test_name)),
disable_write_protection=test_name in exclude_write_protection,
)
mem_segments.append(mmio)

mem_model = CoreMemoryModel(mem_segments)
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