Merge branch 'master' into lekcyjna/add-pytest-2

.github/workflows/main.yml

@@ -40,7 +40,9 @@ jobs:
       - uses: actions/upload-artifact@v3
         with:
           name: "verilog-full-core"
-          path: core.v
+          path: |
+            core.v
+            core.v.json
 
 
   build-riscof-tests:

.gitignore

@@ -15,6 +15,9 @@ venv.bak/
 # Verilog files
 *.v
 
+# Verilog generation debug files
+*.v.json
+
 # Waveform dumps
 *.vcd
 *.gtkw

constants/ecp5_platforms.py

@@ -2,7 +2,7 @@
 from itertools import chain
 from typing import TypeAlias
 from amaranth.build.dsl import Subsignal
-from amaranth.vendor.lattice_ecp5 import LatticeECP5Platform
+from amaranth.vendor import LatticeECP5Platform
 from amaranth.build import Resource, Attrs, Pins, Clock, PinsN
 
 from constants.ecp5_pinout import ecp5_bg756_pins, ecp5_bg756_pclk

coreblocks/cache/icache.py

@@ -2,7 +2,7 @@
 import operator
 
 from amaranth import *
-from amaranth.utils import log2_int
+from amaranth.utils import exact_log2
 
 from transactron.core import def_method, Priority, TModule
 from transactron import Method, Transaction
@@ -52,7 +52,7 @@ def _(addr: Value) -> None:
             m.d.sync += req_addr.eq(addr)
             self.bus_master.request_read(
                 m,
-                addr=addr >> log2_int(self.params.word_width_bytes),
+                addr=addr >> exact_log2(self.params.word_width_bytes),
                 sel=C(1).replicate(self.bus_master.params.data_width // self.bus_master.params.granularity),
             )
 
@@ -350,7 +350,7 @@ def elaborate(self, platform):
 
             # We address the data RAM using machine words, so we have to
             # discard a few least significant bits from the address.
-            redundant_offset_bits = log2_int(self.params.word_width_bytes)
+            redundant_offset_bits = exact_log2(self.params.word_width_bytes)
             rd_addr = Cat(self.data_rd_addr.offset, self.data_rd_addr.index)[redundant_offset_bits:]
             wr_addr = Cat(self.data_wr_addr.offset, self.data_wr_addr.index)[redundant_offset_bits:]
 

coreblocks/cache/refiller.py

@@ -1,10 +1,11 @@
+from amaranth import *
 from coreblocks.cache.icache import CacheRefillerInterface
 from coreblocks.params import ICacheLayouts, ICacheParameters
 from coreblocks.peripherals.bus_adapter import BusMasterInterface
 from transactron.core import Transaction
-from transactron.lib import C, Cat, Elaboratable, Forwarder, Method, Signal, TModule, def_method
+from transactron.lib import Forwarder, Method, TModule, def_method
 
-from amaranth.utils import log2_int
+from amaranth.utils import exact_log2
 
 
 __all__ = ["SimpleCommonBusCacheRefiller"]
@@ -62,7 +63,7 @@ def _():
                 address_fwd.write(m, word_counter=next_word_counter, refill_address=refill_address)
 
             return {
-                "addr": Cat(C(0, log2_int(self.params.word_width_bytes)), word_counter, refill_address),
+                "addr": Cat(C(0, exact_log2(self.params.word_width_bytes)), word_counter, refill_address),
                 "data": fetched.data,
                 "error": fetched.err,
                 "last": last,

coreblocks/frontend/instr_description.py

@@ -164,20 +164,23 @@ class Encoding:
         Encoding(Opcode.OP, Funct3.MIN, Funct7.MIN),
         Encoding(Opcode.OP, Funct3.MINU, Funct7.MIN),
         Encoding(Opcode.OP, Funct3.ORN, Funct7.ORN),
+        Encoding(Opcode.OP, Funct3.XNOR, Funct7.XNOR),
+    ],
+    OpType.BIT_ROTATION: [
         Encoding(Opcode.OP, Funct3.ROL, Funct7.ROL),
         Encoding(Opcode.OP, Funct3.ROR, Funct7.ROR),
         Encoding(Opcode.OP_IMM, Funct3.ROR, Funct7.ROR),
-        Encoding(Opcode.OP, Funct3.XNOR, Funct7.XNOR),
     ],
     OpType.UNARY_BIT_MANIPULATION_1: [
-        Encoding(Opcode.OP_IMM, Funct3.ORCB, funct12=Funct12.ORCB),
         Encoding(Opcode.OP_IMM, Funct3.REV8, funct12=Funct12.REV8_32),
         Encoding(Opcode.OP_IMM, Funct3.SEXTB, funct12=Funct12.SEXTB),
         Encoding(Opcode.OP, Funct3.ZEXTH, funct12=Funct12.ZEXTH),
     ],
-    # Instructions SEXTH, SEXTHB, CPOP, CLZ and CTZ  cannot be distiguished by their Funct7 code
+    # Instructions SEXTH, SEXTHB, CPOP, CLZ and CTZ cannot be distiguished by their Funct7 code
+    # ORCB is here because of optimization to not lookup Funct7 in UNARY_BIT_MANIPULATION_1
     OpType.UNARY_BIT_MANIPULATION_2: [
         Encoding(Opcode.OP_IMM, Funct3.SEXTH, funct12=Funct12.SEXTH),
+        Encoding(Opcode.OP_IMM, Funct3.ORCB, funct12=Funct12.ORCB),
     ],
     OpType.UNARY_BIT_MANIPULATION_3: [
         Encoding(Opcode.OP_IMM, Funct3.CLZ, funct12=Funct12.CLZ),

coreblocks/fu/alu.py

@@ -82,14 +82,14 @@ def get_instructions(self) -> Sequence[tuple]:
                 (self.Fn.MAXU, OpType.BIT_MANIPULATION, Funct3.MAXU, Funct7.MAX),
                 (self.Fn.MIN, OpType.BIT_MANIPULATION, Funct3.MIN, Funct7.MIN),
                 (self.Fn.MINU, OpType.BIT_MANIPULATION, Funct3.MINU, Funct7.MIN),
-                (self.Fn.ORCB, OpType.UNARY_BIT_MANIPULATION_1, Funct3.ORCB, Funct7.ORCB),
-                (self.Fn.REV8, OpType.UNARY_BIT_MANIPULATION_1, Funct3.REV8, Funct7.REV8),
-                (self.Fn.SEXTB, OpType.UNARY_BIT_MANIPULATION_1, Funct3.SEXTB, Funct7.SEXTB),
-                (self.Fn.ZEXTH, OpType.UNARY_BIT_MANIPULATION_1, Funct3.ZEXTH, Funct7.ZEXTH),
-                (self.Fn.CPOP, OpType.UNARY_BIT_MANIPULATION_5, Funct3.CPOP, Funct7.CPOP),
-                (self.Fn.SEXTH, OpType.UNARY_BIT_MANIPULATION_2, Funct3.SEXTH, Funct7.SEXTH),
-                (self.Fn.CLZ, OpType.UNARY_BIT_MANIPULATION_3, Funct3.CLZ, Funct7.CLZ),
-                (self.Fn.CTZ, OpType.UNARY_BIT_MANIPULATION_4, Funct3.CTZ, Funct7.CTZ),
+                (self.Fn.REV8, OpType.UNARY_BIT_MANIPULATION_1, Funct3.REV8),
+                (self.Fn.SEXTB, OpType.UNARY_BIT_MANIPULATION_1, Funct3.SEXTB),
+                (self.Fn.ZEXTH, OpType.UNARY_BIT_MANIPULATION_1, Funct3.ZEXTH),
+                (self.Fn.ORCB, OpType.UNARY_BIT_MANIPULATION_2, Funct3.ORCB),
+                (self.Fn.SEXTH, OpType.UNARY_BIT_MANIPULATION_2, Funct3.SEXTH),
+                (self.Fn.CLZ, OpType.UNARY_BIT_MANIPULATION_3, Funct3.CLZ),
+                (self.Fn.CTZ, OpType.UNARY_BIT_MANIPULATION_4, Funct3.CTZ),
+                (self.Fn.CPOP, OpType.UNARY_BIT_MANIPULATION_5, Funct3.CPOP),
             ]
             * self.zbb_enable
         )

coreblocks/fu/shift_unit.py

@@ -34,8 +34,8 @@ def get_instructions(self) -> Sequence[tuple]:
             (self.Fn.SRL, OpType.SHIFT, Funct3.SR, Funct7.SL),
             (self.Fn.SRA, OpType.SHIFT, Funct3.SR, Funct7.SA),
         ] + [
-            (self.Fn.ROR, OpType.BIT_MANIPULATION, Funct3.ROR, Funct7.ROR),
-            (self.Fn.ROL, OpType.BIT_MANIPULATION, Funct3.ROL, Funct7.ROL),
+            (self.Fn.ROR, OpType.BIT_ROTATION, Funct3.ROR),
+            (self.Fn.ROL, OpType.BIT_ROTATION, Funct3.ROL),
         ] * self.zbb_enable
 
 

coreblocks/lsu/dummyLsu.py

@@ -73,7 +73,7 @@ def postprocess_load_data(self, m: ModuleLike, funct3: Value, raw_data: Value, a
                     m.d.av_comb += data.eq(tmp.as_signed())
                 with m.Else():
                     m.d.av_comb += data.eq(tmp)
-            with m.Case():
+            with m.Default():
                 m.d.av_comb += data.eq(raw_data)
         return data
 
@@ -84,7 +84,7 @@ def prepare_data_to_save(self, m: ModuleLike, funct3: Value, raw_data: Value, ad
                 m.d.av_comb += data.eq(raw_data[0:8] << (addr[0:2] << 3))
             with m.Case(Funct3.H):
                 m.d.av_comb += data.eq(raw_data[0:16] << (addr[1] << 4))
-            with m.Case():
+            with m.Default():
                 m.d.av_comb += data.eq(raw_data)
         return data
 
@@ -95,7 +95,7 @@ def check_align(self, m: TModule, funct3: Value, addr: Value):
                 m.d.av_comb += aligned.eq(addr[0:2] == 0)
             with m.Case(Funct3.H, Funct3.HU):
                 m.d.av_comb += aligned.eq(addr[0] == 0)
-            with m.Case():
+            with m.Default():
                 m.d.av_comb += aligned.eq(1)
         return aligned
 

coreblocks/params/genparams.py

@@ -1,6 +1,6 @@
 from __future__ import annotations
 
-from amaranth.utils import log2_int
+from amaranth.utils import exact_log2
 
 from .isa import ISA, gen_isa_string
 from .icache_params import ICacheParameters
@@ -36,7 +36,7 @@ def __init__(self, cfg: CoreConfiguration):
 
         bytes_in_word = self.isa.xlen // 8
         self.wb_params = WishboneParameters(
-            data_width=self.isa.xlen, addr_width=self.isa.xlen - log2_int(bytes_in_word)
+            data_width=self.isa.xlen, addr_width=self.isa.xlen - exact_log2(bytes_in_word)
         )
 
         self.icache_params = ICacheParameters(

coreblocks/params/instr.py

@@ -1,6 +1,6 @@
 from abc import abstractmethod, ABC
 
-from amaranth.hdl.ast import ValueCastable
+from amaranth.hdl import ValueCastable
 from amaranth import *
 
 from transactron.utils import ValueLike

coreblocks/params/optypes.py

@@ -34,6 +34,7 @@ class OpType(IntEnum):
     SINGLE_BIT_MANIPULATION = auto()
     ADDRESS_GENERATION = auto()
     BIT_MANIPULATION = auto()
+    BIT_ROTATION = auto()
     UNARY_BIT_MANIPULATION_1 = auto()
     UNARY_BIT_MANIPULATION_2 = auto()
     UNARY_BIT_MANIPULATION_3 = auto()
@@ -88,6 +89,7 @@ class OpType(IntEnum):
     ],
     Extension.ZBB: [
         OpType.BIT_MANIPULATION,
+        OpType.BIT_ROTATION,
         OpType.UNARY_BIT_MANIPULATION_1,
         OpType.UNARY_BIT_MANIPULATION_2,
         OpType.UNARY_BIT_MANIPULATION_3,

requirements.txt

@@ -1,3 +1,3 @@
 amaranth-yosys==0.35.0.0.post81
-git+https://github.com/amaranth-lang/amaranth@94c504afc7d81738ecdc9523a2615ef43ecbf51a
+git+https://github.com/amaranth-lang/amaranth@115954b4d957b4ba642ad056ab1670bf5d185fb6
 dataclasses-json==0.6.3

scripts/gen_verilog.py

@@ -4,10 +4,11 @@
 import sys
 import argparse
 
+from amaranth import *
 from amaranth.build import Platform
-from amaranth.back import verilog
 from amaranth import Module, Elaboratable
 
+
 if __name__ == "__main__":
     parent = os.path.dirname(os.path.dirname(os.path.abspath(__file__)))
     sys.path.insert(0, parent)
@@ -16,8 +17,8 @@
 from coreblocks.peripherals.wishbone import WishboneBus
 from coreblocks.core import Core
 from transactron import TransactionModule
-from transactron.utils import flatten_signals
-from transactron.utils.dependencies import DependencyManager, DependencyContext
+from transactron.utils import flatten_signals, DependencyManager, DependencyContext
+from transactron.utils.gen import generate_verilog
 
 from coreblocks.params.configurations import *
 
@@ -44,14 +45,17 @@ def elaborate(self, platform: Platform):
         return tm
 
 
-def gen_verilog(core_config: CoreConfiguration, output_path):
+def gen_verilog(core_config: CoreConfiguration, output_path: str):
     with DependencyContext(DependencyManager()):
-        top = Top(GenParams(core_config))
+        gp = GenParams(core_config)
+        top = Top(gp)
+        ports = list(flatten_signals(top.wb_instr)) + list(flatten_signals(top.wb_data))
 
-        with open(output_path, "w") as f:
-            signals = list(flatten_signals(top.wb_instr)) + list(flatten_signals(top.wb_data))
+        verilog_text, gen_info = generate_verilog(top, ports)
 
-            f.write(verilog.convert(top, ports=signals, strip_internal_attrs=True))
+        gen_info.encode(f"{output_path}.json")
+        with open(output_path, "w") as f:
+            f.write(verilog_text)
 
 
 def main():

scripts/run_benchmarks.py

@@ -61,7 +61,10 @@ def run_benchmarks_with_cocotb(benchmarks: list[str], traces: bool) -> bool:
     arglist += [f"TESTCASE={test_cases}"]
 
     verilog_code = topdir.joinpath("core.v")
+    gen_info_path = f"{verilog_code}.json"
+
     arglist += [f"VERILOG_SOURCES={verilog_code}"]
+    arglist += [f"_COREBLOCKS_GEN_INFO={gen_info_path}"]
 
     if traces:
         arglist += ["TRACES=1"]

scripts/run_signature.py

@@ -32,7 +32,10 @@ def run_with_cocotb(test_name: str, traces: bool, output: str) -> bool:
     arglist += [f"OUTPUT={output}"]
 
     verilog_code = f"{parent}/core.v"
+    gen_info_path = f"{verilog_code}.json"
+
     arglist += [f"VERILOG_SOURCES={verilog_code}"]
+    arglist += [f"_COREBLOCKS_GEN_INFO={gen_info_path}"]
 
     if traces:
         arglist += ["TRACES=1"]

stubs/amaranth/_unused.pyi

@@ -0,0 +1,13 @@
+import sys
+import warnings
+
+__all__ = ["UnusedMustUse", "MustUse"]
+
+
+class UnusedMustUse(Warning):
+    pass
+
+
+class MustUse:
+    _MustUse__silence : bool
+    _MustUse__warning : UnusedMustUse

stubs/amaranth/build/res.pyi

@@ -3,7 +3,7 @@ This type stub file was generated by pyright.
 """
 
 from typing import Any
-from ..hdl.ast import *
+from ..hdl._ast import *
 from ..hdl.rec import *
 from ..lib.io import *
 from .dsl import *

stubs/amaranth/hdl/__init__.pyi

@@ -1,13 +1,29 @@
-"""
-This type stub file was generated by pyright.
-"""
-
-from .ast import Array, C, Cat, ClockSignal, Const, Mux, Repl, ResetSignal, Shape, Signal, Value, signed, unsigned
-from .dsl import Module
-from .cd import ClockDomain
-from .ir import Elaboratable, Fragment, Instance
-from .mem import Memory
+from ._ast import Shape, unsigned, signed, ShapeCastable, ShapeLike
+from ._ast import Value, ValueCastable, ValueLike
+from ._ast import Const, C, Mux, Cat, Array, Signal, ClockSignal, ResetSignal
+from ._dsl import SyntaxError, SyntaxWarning, Module
+from ._cd import DomainError, ClockDomain
+from ._ir import UnusedElaboratable, Elaboratable, DriverConflict, Fragment, Instance
+from ._mem import Memory, ReadPort, WritePort, DummyPort
 from .rec import Record
-from .xfrm import DomainRenamer, EnableInserter, ResetInserter
+from ._xfrm import DomainRenamer, ResetInserter, EnableInserter
+
 
-__all__ = ["Shape", "unsigned", "signed", "Value", "Const", "C", "Mux", "Cat", "Repl", "Array", "Signal", "ClockSignal", "ResetSignal", "Module", "ClockDomain", "Elaboratable", "Fragment", "Instance", "Memory", "Record", "DomainRenamer", "ResetInserter", "EnableInserter"]
+__all__ = [
+    # _ast
+    "Shape", "unsigned", "signed", "ShapeCastable", "ShapeLike",
+    "Value", "ValueCastable", "ValueLike",
+    "Const", "C", "Mux", "Cat", "Array", "Signal", "ClockSignal", "ResetSignal",
+    # _dsl
+    "SyntaxError", "SyntaxWarning", "Module",
+    # _cd
+    "DomainError", "ClockDomain",
+    # _ir
+    "UnusedElaboratable", "Elaboratable", "DriverConflict", "Fragment", "Instance",
+    # _mem
+    "Memory", "ReadPort", "WritePort", "DummyPort",
+    # _rec
+    "Record",
+    # _xfrm
+    "DomainRenamer", "ResetInserter", "EnableInserter",
+]

stubs/amaranth/hdl/ir.pyi → stubs/amaranth/hdl/_ir.pyi

@@ -3,13 +3,17 @@ This type stub file was generated by pyright.
 """
 
 from abc import abstractmethod
-from .ast import *
-from .cd import *
+from ._ast import *
+from ._cd import *
+from .. import _unused
 from transactron.utils import HasElaborate
 
-__all__ = ["Elaboratable", "DriverConflict", "Fragment", "Instance"]
+__all__ = ["UnusedElaboratable", "Elaboratable", "DriverConflict", "Fragment", "Instance"]
 
 
+class UnusedElaboratable(_unused.UnusedMustUse):
+    ...
+
 class Elaboratable():
     @abstractmethod
     def elaborate(self, platform) -> HasElaborate: