Update Transactron

coreblocks/backend/retirement.py

@@ -58,14 +58,10 @@ def __init__(
 
         layouts = self.gen_params.get(RetirementLayouts)
         self.dependency_manager = DependencyContext.get()
-        self.core_state = Method(o=self.gen_params.get(RetirementLayouts).core_state, nonexclusive=True)
+        self.core_state = Method(o=self.gen_params.get(RetirementLayouts).core_state)
         self.dependency_manager.add_dependency(CoreStateKey(), self.core_state)
 
-        # The argument is only used in argument validation, it is not needed in the method body.
-        # A dummy combiner is provided.
-        self.precommit = Method(
-            i=layouts.precommit_in, o=layouts.precommit_out, nonexclusive=True, combiner=lambda m, args, runs: 0
-        )
+        self.precommit = Method(i=layouts.precommit_in, o=layouts.precommit_out)
         self.dependency_manager.add_dependency(InstructionPrecommitKey(), self.precommit)
 
     def elaborate(self, platform):
@@ -239,13 +235,21 @@ def flush_instr(rob_entry):
         # Disable executing any side effects from instructions in core when it is flushed
         m.d.comb += side_fx.eq(~fsm.ongoing("TRAP_FLUSH"))
 
-        @def_method(m, self.core_state)
+        @def_method(m, self.core_state, nonexclusive=True)
         def _():
             return {"flushing": core_flushing}
 
         rob_id_val = Signal(self.gen_params.rob_entries_bits)
 
-        @def_method(m, self.precommit, validate_arguments=lambda rob_id: rob_id == rob_id_val)
+        # The argument is only used in argument validation, it is not needed in the method body.
+        # A dummy combiner is provided.
+        @def_method(
+            m,
+            self.precommit,
+            validate_arguments=lambda rob_id: rob_id == rob_id_val,
+            nonexclusive=True,
+            combiner=lambda m, args, runs: 0,
+        )
         def _(rob_id):
             m.d.top_comb += rob_id_val.eq(self.rob_peek(m).rob_id)
             return {"side_fx": side_fx}

coreblocks/core_structs/rob.py

@@ -14,12 +14,12 @@ def __init__(self, gen_params: GenParams) -> None:
         layouts = gen_params.get(ROBLayouts)
         self.put = Method(i=layouts.data_layout, o=layouts.id_layout)
         self.mark_done = Method(i=layouts.mark_done_layout)
-        self.peek = Method(o=layouts.peek_layout, nonexclusive=True)
+        self.peek = Method(o=layouts.peek_layout)
         self.retire = Method()
         self.done = Array(Signal() for _ in range(2**self.params.rob_entries_bits))
         self.exception = Array(Signal() for _ in range(2**self.params.rob_entries_bits))
         self.data = memory.Memory(shape=layouts.data_layout, depth=2**self.params.rob_entries_bits, init=[])
-        self.get_indices = Method(o=layouts.get_indices, nonexclusive=True)
+        self.get_indices = Method(o=layouts.get_indices)
 
         self.perf_rob_wait_time = FIFOLatencyMeasurer(
             "backend.rob.wait_time",
@@ -51,7 +51,7 @@ def elaborate(self, platform):
 
         m.d.comb += read_port.addr.eq(start_idx)
 
-        @def_method(m, self.peek, ready=peek_possible)
+        @def_method(m, self.peek, ready=peek_possible, nonexclusive=True)
         def _():
             return {
                 "rob_data": read_port.data,
@@ -83,7 +83,7 @@ def _(rob_id: Value, exception):
             m.d.sync += self.done[rob_id].eq(1)
             m.d.sync += self.exception[rob_id].eq(exception)
 
-        @def_method(m, self.get_indices)
+        @def_method(m, self.get_indices, nonexclusive=True)
         def _():
             return {"start": start_idx, "end": end_idx}
 

coreblocks/func_blocks/fu/common/rs.py

@@ -42,7 +42,7 @@ def __init__(
         self.take = Method(i=self.layouts.take_in, o=self.layouts.take_out)
 
         self.ready_for = [list(op_list) for op_list in ready_for]
-        self.get_ready_list = [Method(o=self.layouts.get_ready_list_out, nonexclusive=True) for _ in self.ready_for]
+        self.get_ready_list = [Method(o=self.layouts.get_ready_list_out) for _ in self.ready_for]
 
         self.data = Array(Signal(self.internal_layout) for _ in range(self.rs_entries))
         self.data_ready = Signal(self.rs_entries)
@@ -113,7 +113,7 @@ def _(rs_entry_id: Value) -> RecordDict:
 
         for get_ready_list, ready_list in zip(self.get_ready_list, ready_lists):
 
-            @def_method(m, get_ready_list, ready=ready_list.any())
+            @def_method(m, get_ready_list, ready=ready_list.any(), nonexclusive=True)
             def _() -> RecordDict:
                 return {"ready_list": ready_list}
 

coreblocks/func_blocks/fu/lsu/dummyLsu.py

@@ -44,7 +44,7 @@ def __init__(self, gen_params: GenParams, bus: BusMasterInterface) -> None:
         self.dependency_manager = DependencyContext.get()
         self.report = self.dependency_manager.get_dependency(ExceptionReportKey())
 
-        self.issue = Method(i=self.fu_layouts.issue, single_caller=True)
+        self.issue = Method(i=self.fu_layouts.issue)
         self.accept = Method(o=self.fu_layouts.accept)
 
         self.bus = bus
@@ -73,7 +73,7 @@ def elaborate(self, platform):
         m.submodules.issued = issued = FIFO(self.fu_layouts.issue, 2)
         m.submodules.issued_noop = issued_noop = FIFO(self.fu_layouts.issue, 2)
 
-        @def_method(m, self.issue)
+        @def_method(m, self.issue, single_caller=True)
         def _(arg):
             self.log.debug(
                 m, 1, "issue rob_id={} funct3={} op_type={}", arg.rob_id, arg.exec_fn.funct3, arg.exec_fn.op_type

coreblocks/priv/csr/csr_register.py

@@ -109,8 +109,8 @@ def __init__(
 
         csr_layouts = gen_params.get(CSRRegisterLayouts, data_width=self.width)
 
-        self.read = Method(o=csr_layouts.read, nonexclusive=True)
-        self.read_comb = Method(o=csr_layouts.read, nonexclusive=True)
+        self.read = Method(o=csr_layouts.read)
+        self.read_comb = Method(o=csr_layouts.read)
         self.write = Method(i=csr_layouts.write)
 
         self._internal_fu_read = Method(o=csr_layouts._fu_read)
@@ -162,7 +162,7 @@ def _(data):
             m.d.comb += fu_write_internal.active.eq(1)
             m.d.sync += self.side_effects.write.eq(1)
 
-        @def_method(m, self.read)
+        @def_method(m, self.read, nonexclusive=True)
         def _():
             return {"data": self.value, "read": self.side_effects.read, "written": self.side_effects.write}
 
@@ -171,7 +171,7 @@ def _():
             m.d.sync += self.side_effects.read.eq(1)
             return self.value
 
-        @def_method(m, self.read_comb)
+        @def_method(m, self.read_comb, nonexclusive=True)
         def _():
             return {
                 "data": Mux(self._internal_fu_write.run, fu_write_internal.data, self.value),

coreblocks/priv/traps/exception.py

@@ -67,7 +67,7 @@ def __init__(self, gen_params: GenParams, rob_get_indices: Method, fetch_stall_e
         dm = DependencyContext.get()
         dm.add_dependency(ExceptionReportKey(), self.report)
 
-        self.get = Method(o=self.layouts.get, nonexclusive=True)
+        self.get = Method(o=self.layouts.get)
 
         self.clear = Method()
 
@@ -109,7 +109,7 @@ def _(cause, rob_id, pc, mtval):
             # In case of any reported exception, core will need to be flushed. Fetch can be stalled immediately
             self.fetch_stall_exception(m)
 
-        @def_method(m, self.get)
+        @def_method(m, self.get, nonexclusive=True)
         def _():
             return {"rob_id": self.rob_id, "cause": self.cause, "pc": self.pc, "mtval": self.mtval, "valid": self.valid}
 

requirements.txt

@@ -2,4 +2,4 @@ amaranth==0.5.3
 amaranth-stubs @ git+https://github.com/kuznia-rdzeni/amaranth-stubs.git@edb302b001433edf4c8568190adc9bd0c0039f45
 amaranth-yosys==0.40.0.0.post100
 dataclasses-json==0.6.3
-transactron @ git+https://github.com/kuznia-rdzeni/transactron.git@6520af4774f198c998a28ec0eb9ad198e04b4508
+transactron @ git+https://github.com/kuznia-rdzeni/transactron.git@c443ebb60521d87d4553efc1c5e86fda8707d69d  # TODO: merge and change to master

test/backend/test_annoucement.py

@@ -49,11 +49,11 @@ def elaborate(self, platform):
         )
 
         # Create stubs for interfaces used by result announcement
-        self.rs_announce_val_tbio = TestbenchIO(Adapter(i=self.lay_rs_write, o=self.lay_rs_write))
+        self.rs_announce_val_tbio = TestbenchIO(Adapter.create(i=self.lay_rs_write, o=self.lay_rs_write))
         m.submodules.rs_announce_val_tbio = self.rs_announce_val_tbio
-        self.rf_announce_val_tbio = TestbenchIO(Adapter(i=self.lay_rf_write, o=self.lay_rf_write))
+        self.rf_announce_val_tbio = TestbenchIO(Adapter.create(i=self.lay_rf_write, o=self.lay_rf_write))
         m.submodules.rf_announce_val_tbio = self.rf_announce_val_tbio
-        self.rob_mark_done_tbio = TestbenchIO(Adapter(i=self.lay_rob_mark_done, o=self.lay_rob_mark_done))
+        self.rob_mark_done_tbio = TestbenchIO(Adapter.create(i=self.lay_rob_mark_done, o=self.lay_rob_mark_done))
         m.submodules.rob_mark_done_tbio = self.rob_mark_done_tbio
 
         # Create result announcement

test/backend/test_retirement.py

@@ -41,28 +41,30 @@ def elaborate(self, platform):
         )
 
         m.submodules.mock_rob_peek = self.mock_rob_peek = TestbenchIO(
-            Adapter(o=rob_layouts.peek_layout, nonexclusive=True)
+            Adapter.create(o=rob_layouts.peek_layout, nonexclusive=True)
         )
 
-        m.submodules.mock_rob_retire = self.mock_rob_retire = TestbenchIO(Adapter())
+        m.submodules.mock_rob_retire = self.mock_rob_retire = TestbenchIO(Adapter.create())
 
-        m.submodules.mock_rf_free = self.mock_rf_free = TestbenchIO(Adapter(i=rf_layouts.rf_free))
+        m.submodules.mock_rf_free = self.mock_rf_free = TestbenchIO(Adapter.create(i=rf_layouts.rf_free))
 
         m.submodules.mock_exception_cause = self.mock_exception_cause = TestbenchIO(
-            Adapter(o=exception_layouts.get, nonexclusive=True)
+            Adapter.create(o=exception_layouts.get, nonexclusive=True)
         )
-        m.submodules.mock_exception_clear = self.mock_exception_clear = TestbenchIO(Adapter())
+        m.submodules.mock_exception_clear = self.mock_exception_clear = TestbenchIO(Adapter.create())
 
         m.submodules.generic_csr = self.generic_csr = GenericCSRRegisters(self.gen_params)
         DependencyContext.get().add_dependency(CSRInstancesKey(), self.generic_csr)
 
-        m.submodules.mock_fetch_continue = self.mock_fetch_continue = TestbenchIO(Adapter(i=fetch_layouts.resume))
+        m.submodules.mock_fetch_continue = self.mock_fetch_continue = TestbenchIO(
+            Adapter.create(i=fetch_layouts.resume)
+        )
         m.submodules.mock_instr_decrement = self.mock_instr_decrement = TestbenchIO(
-            Adapter(o=core_instr_counter_layouts.decrement)
+            Adapter.create(o=core_instr_counter_layouts.decrement)
         )
-        m.submodules.mock_trap_entry = self.mock_trap_entry = TestbenchIO(Adapter())
+        m.submodules.mock_trap_entry = self.mock_trap_entry = TestbenchIO(Adapter.create())
         m.submodules.mock_async_interrupt_cause = self.mock_async_interrupt_cause = TestbenchIO(
-            Adapter(o=interrupt_controller_layouts.interrupt_cause)
+            Adapter.create(o=interrupt_controller_layouts.interrupt_cause)
         )
 
         m.submodules.retirement = self.retirement = Retirement(

test/cache/test_icache.py

@@ -255,8 +255,8 @@ class MockedCacheRefiller(Elaboratable, CacheRefillerInterface):
     def __init__(self, gen_params: GenParams):
         layouts = gen_params.get(ICacheLayouts)
 
-        self.start_refill_mock = TestbenchIO(Adapter(i=layouts.start_refill))
-        self.accept_refill_mock = TestbenchIO(Adapter(o=layouts.accept_refill))
+        self.start_refill_mock = TestbenchIO(Adapter.create(i=layouts.start_refill))
+        self.accept_refill_mock = TestbenchIO(Adapter.create(o=layouts.accept_refill))
 
         self.start_refill = self.start_refill_mock.adapter.iface
         self.accept_refill = self.accept_refill_mock.adapter.iface

test/frontend/test_fetch.py

@@ -34,8 +34,8 @@ class MockedICache(Elaboratable, CacheInterface):
     def __init__(self, gen_params: GenParams):
         layouts = gen_params.get(ICacheLayouts)
 
-        self.issue_req_io = TestbenchIO(Adapter(i=layouts.issue_req))
-        self.accept_res_io = TestbenchIO(Adapter(o=layouts.accept_res))
+        self.issue_req_io = TestbenchIO(Adapter.create(i=layouts.issue_req))
+        self.accept_res_io = TestbenchIO(Adapter.create(o=layouts.accept_res))
 
         self.issue_req = self.issue_req_io.adapter.iface
         self.accept_res = self.accept_res_io.adapter.iface
@@ -78,7 +78,7 @@ def setup(self, fixture_initialize_testing_env):
         fifo = BasicFifo(self.gen_params.get(FetchLayouts).raw_instr, depth=2)
         self.io_out = TestbenchIO(AdapterTrans(fifo.read))
         self.clean_fifo = TestbenchIO(AdapterTrans(fifo.clear))
-        self.fetch_resume_mock = TestbenchIO(Adapter())
+        self.fetch_resume_mock = TestbenchIO(Adapter.create())
         DependencyContext.get().add_dependency(FetchResumeKey(), self.fetch_resume_mock.adapter.iface)
 
         self.fetch = SimpleTestCircuit(FetchUnit(self.gen_params, self.icache, fifo.write))

test/func_blocks/csr/test_csr.py

@@ -33,7 +33,7 @@ def elaborate(self, platform):
         m = Module()
 
         m.submodules.precommit = self.precommit = TestbenchIO(
-            Adapter(
+            Adapter.create(
                 i=self.gen_params.get(RetirementLayouts).precommit_in,
                 o=self.gen_params.get(RetirementLayouts).precommit_out,
                 nonexclusive=True,
@@ -49,7 +49,7 @@ def elaborate(self, platform):
         m.submodules.update = self.update = TestbenchIO(AdapterTrans(self.dut.update))
         m.submodules.accept = self.accept = TestbenchIO(AdapterTrans(self.dut.get_result))
         m.submodules.exception_report = self.exception_report = TestbenchIO(
-            Adapter(i=self.gen_params.get(ExceptionRegisterLayouts).report)
+            Adapter.create(i=self.gen_params.get(ExceptionRegisterLayouts).report)
         )
         m.submodules.csr_instances = self.csr_instances = GenericCSRRegisters(self.gen_params)
         m.submodules.priv_io = self.priv_io = TestbenchIO(AdapterTrans(self.csr_instances.m_mode.priv_mode.write))

test/func_blocks/fu/functional_common.py

@@ -106,7 +106,7 @@ def compute_result(i1: int, i2: int, i_imm: int, pc: int, fn: _T, xlen: int) ->
     def setup(self, fixture_initialize_testing_env):
         self.gen_params = GenParams(test_core_config)
 
-        self.report_mock = TestbenchIO(Adapter(i=self.gen_params.get(ExceptionRegisterLayouts).report))
+        self.report_mock = TestbenchIO(Adapter.create(i=self.gen_params.get(ExceptionRegisterLayouts).report))
         self.csrs = GenericCSRRegisters(self.gen_params)
 
         DependencyContext.get().add_dependency(ExceptionReportKey(), self.report_mock.adapter.iface)

test/func_blocks/lsu/test_dummylsu.py

@@ -73,14 +73,14 @@ def elaborate(self, platform):
         self.bus_master_adapter = MockMasterAdapter(bus_mock_params)
 
         m.submodules.exception_report = self.exception_report = TestbenchIO(
-            Adapter(i=self.gen.get(ExceptionRegisterLayouts).report)
+            Adapter.create(i=self.gen.get(ExceptionRegisterLayouts).report)
         )
 
         DependencyContext.get().add_dependency(ExceptionReportKey(), self.exception_report.adapter.iface)
 
         layouts = self.gen.get(RetirementLayouts)
         m.submodules.precommit = self.precommit = TestbenchIO(
-            Adapter(
+            Adapter.create(
                 i=layouts.precommit_in,
                 o=layouts.precommit_out,
                 nonexclusive=True,
@@ -89,7 +89,7 @@ def elaborate(self, platform):
         )
         DependencyContext.get().add_dependency(InstructionPrecommitKey(), self.precommit.adapter.iface)
 
-        m.submodules.core_state = self.core_state = TestbenchIO(Adapter(o=layouts.core_state, nonexclusive=True))
+        m.submodules.core_state = self.core_state = TestbenchIO(Adapter.create(o=layouts.core_state, nonexclusive=True))
         DependencyContext.get().add_dependency(CoreStateKey(), self.core_state.adapter.iface)
 
         m.submodules.func_unit = func_unit = LSUDummy(self.gen, self.bus_master_adapter)

test/func_blocks/lsu/test_pma.py

@@ -53,14 +53,14 @@ def elaborate(self, platform):
         self.bus_master_adapter = MockMasterAdapter(bus_mock_params)
 
         m.submodules.exception_report = self.exception_report = TestbenchIO(
-            Adapter(i=self.gen.get(ExceptionRegisterLayouts).report)
+            Adapter.create(i=self.gen.get(ExceptionRegisterLayouts).report)
         )
 
         DependencyContext.get().add_dependency(ExceptionReportKey(), self.exception_report.adapter.iface)
 
         layouts = self.gen.get(RetirementLayouts)
         m.submodules.precommit = self.precommit = TestbenchIO(
-            Adapter(
+            Adapter.create(
                 i=layouts.precommit_in,
                 o=layouts.precommit_out,
                 nonexclusive=True,
@@ -69,7 +69,7 @@ def elaborate(self, platform):
         )
         DependencyContext.get().add_dependency(InstructionPrecommitKey(), self.precommit.adapter.iface)
 
-        m.submodules.core_state = self.core_state = TestbenchIO(Adapter(o=layouts.core_state, nonexclusive=True))
+        m.submodules.core_state = self.core_state = TestbenchIO(Adapter.create(o=layouts.core_state, nonexclusive=True))
         DependencyContext.get().add_dependency(CoreStateKey(), self.core_state.adapter.iface)
 
         m.submodules.func_unit = func_unit = LSUDummy(self.gen, self.bus_master_adapter)

test/peripherals/bus_mock.py

@@ -21,10 +21,10 @@ def __init__(self, params: BusMockParameters):
         self.params = params
         self.method_layouts = CommonBusMasterMethodLayout(params)
 
-        self.request_read_mock = TestbenchIO(Adapter(i=self.method_layouts.request_read_layout))
-        self.request_write_mock = TestbenchIO(Adapter(i=self.method_layouts.request_write_layout))
-        self.get_read_response_mock = TestbenchIO(Adapter(o=self.method_layouts.read_response_layout))
-        self.get_write_response_mock = TestbenchIO(Adapter(o=self.method_layouts.write_response_layout))
+        self.request_read_mock = TestbenchIO(Adapter.create(i=self.method_layouts.request_read_layout))
+        self.request_write_mock = TestbenchIO(Adapter.create(i=self.method_layouts.request_write_layout))
+        self.get_read_response_mock = TestbenchIO(Adapter.create(o=self.method_layouts.read_response_layout))
+        self.get_write_response_mock = TestbenchIO(Adapter.create(o=self.method_layouts.write_response_layout))
         self.request_read = self.request_read_mock.adapter.iface
         self.request_write = self.request_write_mock.adapter.iface
         self.get_read_response = self.get_read_response_mock.adapter.iface

test/priv/traps/test_exception.py

@@ -33,8 +33,8 @@ def test_randomized(self):
 
         self.cycles = 256
 
-        self.rob_idx_mock = TestbenchIO(Adapter(o=self.gen_params.get(ROBLayouts).get_indices))
-        self.fetch_stall_mock = TestbenchIO(Adapter())
+        self.rob_idx_mock = TestbenchIO(Adapter.create(o=self.gen_params.get(ROBLayouts).get_indices))
+        self.fetch_stall_mock = TestbenchIO(Adapter.create())
         self.dut = SimpleTestCircuit(
             ExceptionInformationRegister(
                 self.gen_params, self.rob_idx_mock.adapter.iface, self.fetch_stall_mock.adapter.iface

test/scheduler/test_rs_selection.py

@@ -36,10 +36,10 @@ def elaborate(self, platform):
         # mocked input and output
         m.submodules.instr_in = self.instr_in = TestbenchIO(AdapterTrans(instr_fifo.write))
         m.submodules.instr_out = self.instr_out = TestbenchIO(AdapterTrans(out_fifo.read))
-        m.submodules.rs1_alloc = self.rs1_alloc = TestbenchIO(Adapter(o=rs_layouts.rs.select_out))
-        m.submodules.rs2_alloc = self.rs2_alloc = TestbenchIO(Adapter(o=rs_layouts.rs.select_out))
-        m.submodules.rf_read_req1 = self.rf_read_req1 = TestbenchIO(Adapter(i=rf_layouts.rf_read_in))
-        m.submodules.rf_read_req2 = self.rf_read_req2 = TestbenchIO(Adapter(i=rf_layouts.rf_read_in))
+        m.submodules.rs1_alloc = self.rs1_alloc = TestbenchIO(Adapter.create(o=rs_layouts.rs.select_out))
+        m.submodules.rs2_alloc = self.rs2_alloc = TestbenchIO(Adapter.create(o=rs_layouts.rs.select_out))
+        m.submodules.rf_read_req1 = self.rf_read_req1 = TestbenchIO(Adapter.create(i=rf_layouts.rf_read_in))
+        m.submodules.rf_read_req2 = self.rf_read_req2 = TestbenchIO(Adapter.create(i=rf_layouts.rf_read_in))
 
         # rs selector
         m.submodules.selector = self.selector = RSSelection(