Merge branch 'master' into asm-linker

kuznia-rdzeni · Nov 24, 2023 · e4202c9 · e4202c9
2 parents 4d7cecc + 964065c
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diff --git a/docs/Current_graph.md b/docs/Current_graph.md
diff --git a/docs/Assumptions.md → docs/assumptions.md b/docs/Assumptions.md → docs/assumptions.md
diff --git a/docs/current-graph.md b/docs/current-graph.md
@@ -0,0 +1,12 @@
+# Full transaction-method graph
+
+<div style="overflow: scroll; white-space: nowrap">
+<div style="width: 2000%; height: 2000%">
+
+   ```{eval-rst}
+   .. include:: auto_graph.rst
+      
+   ```
+
+</div>
+</div>
diff --git a/docs/Development_environment.md → docs/development-environment.md b/docs/Development_environment.md → docs/development-environment.md
diff --git a/docs/Home.md → docs/home.md b/docs/Home.md → docs/home.md
diff --git a/docs/index.md b/docs/index.md
@@ -5,17 +5,17 @@
 maxdepth: 3
 ---
 
-Home.md
-Assumptions.md
-Development_environment.md
-Transactions.md
-scheduler/Overview.md
-shared_structs/Implementation/RS_impl.md
-shared_structs/RS.md
-Current_graph.md
-Problem-checklist.md
-synthesis/Synthesis.md
+home.md
+assumptions.md
+development-environment.md
+transactions.md
+scheduler/overview.md
+shared-structs/implementation/rs-impl.md
+shared-structs/rs.md
+current-graph.md
+problem-checklist.md
+synthesis/synthesis.md
 components/icache.md
-miscellany/exceptionsSummary.md
+miscellany/exceptions-summary.md
 api.md
 ```
diff --git a/docs/miscellany/exceptionsSummary.md → docs/miscellany/exceptions-summary.md b/docs/miscellany/exceptionsSummary.md → docs/miscellany/exceptions-summary.md
diff --git a/docs/Problem-checklist.md → docs/problem-checklist.md b/docs/Problem-checklist.md → docs/problem-checklist.md
diff --git a/docs/scheduler/Overview.md → docs/scheduler/overview.md b/docs/scheduler/Overview.md → docs/scheduler/overview.md
diff --git a/.../shared_structs/Implementation/RS_impl.md → .../shared-structs/implementation/rs-impl.md b/.../shared_structs/Implementation/RS_impl.md → .../shared-structs/implementation/rs-impl.md
diff --git a/docs/shared_structs/RS.md → docs/shared-structs/rs.md b/docs/shared_structs/RS.md → docs/shared-structs/rs.md
diff --git a/docs/synthesis/Synthesis.md → docs/synthesis/synthesis.md b/docs/synthesis/Synthesis.md → docs/synthesis/synthesis.md
diff --git a/docs/Transactions.md → docs/transactions.md b/docs/Transactions.md → docs/transactions.md
diff --git a/test/structs_common/test_rat.py b/test/structs_common/test_rat.py
@@ -0,0 +1,85 @@
+from ..common import TestCaseWithSimulator, SimpleTestCircuit
+
+from coreblocks.structs_common.rat import FRAT, RRAT
+from coreblocks.params import GenParams
+from coreblocks.params.configurations import test_core_config
+
+from collections import deque
+from random import Random
+
+
+class TestFrontendRegisterAliasTable(TestCaseWithSimulator):
+    def gen_input(self):
+        for _ in range(self.test_steps):
+            rl = self.rand.randrange(self.gen_params.isa.reg_cnt)
+            rp = self.rand.randrange(1, 2**self.gen_params.phys_regs_bits) if rl != 0 else 0
+            rl_s1 = self.rand.randrange(self.gen_params.isa.reg_cnt)
+            rl_s2 = self.rand.randrange(self.gen_params.isa.reg_cnt)
+
+            self.to_execute_list.append({"rl": rl, "rp": rp, "rl_s1": rl_s1, "rl_s2": rl_s2})
+
+    def do_rename(self):
+        for _ in range(self.test_steps):
+            to_execute = self.to_execute_list.pop()
+            res = yield from self.m.rename.call(
+                rl_dst=to_execute["rl"], rp_dst=to_execute["rp"], rl_s1=to_execute["rl_s1"], rl_s2=to_execute["rl_s2"]
+            )
+            self.assertEqual(res["rp_s1"], self.expected_entries[to_execute["rl_s1"]])
+            self.assertEqual(res["rp_s2"], self.expected_entries[to_execute["rl_s2"]])
+
+            self.expected_entries[to_execute["rl"]] = to_execute["rp"]
+
+    def test_single(self):
+        self.rand = Random(0)
+        self.test_steps = 2000
+        self.gen_params = GenParams(test_core_config.replace(phys_regs_bits=5, rob_entries_bits=6))
+        m = SimpleTestCircuit(FRAT(gen_params=self.gen_params))
+        self.m = m
+
+        self.log_regs = self.gen_params.isa.reg_cnt
+        self.phys_regs = 2**self.gen_params.phys_regs_bits
+
+        self.to_execute_list = deque()
+        self.expected_entries = [0 for _ in range(self.log_regs)]
+
+        self.gen_input()
+        with self.run_simulation(m) as sim:
+            sim.add_sync_process(self.do_rename)
+
+
+class TestRetirementRegisterAliasTable(TestCaseWithSimulator):
+    def gen_input(self):
+        for _ in range(self.test_steps):
+            rl = self.rand.randrange(self.gen_params.isa.reg_cnt)
+            rp = self.rand.randrange(1, 2**self.gen_params.phys_regs_bits) if rl != 0 else 0
+            side_fx = self.rand.randrange(0, 2)
+
+            self.to_execute_list.append({"rl": rl, "rp": rp, "side_fx": side_fx})
+
+    def do_commit(self):
+        for _ in range(self.test_steps):
+            to_execute = self.to_execute_list.pop()
+            res = yield from self.m.commit.call(
+                rl_dst=to_execute["rl"], rp_dst=to_execute["rp"], side_fx=to_execute["side_fx"]
+            )
+            self.assertEqual(res["old_rp_dst"], self.expected_entries[to_execute["rl"]])
+
+            if to_execute["side_fx"]:
+                self.expected_entries[to_execute["rl"]] = to_execute["rp"]
+
+    def test_single(self):
+        self.rand = Random(0)
+        self.test_steps = 2000
+        self.gen_params = GenParams(test_core_config.replace(phys_regs_bits=5, rob_entries_bits=6))
+        m = SimpleTestCircuit(RRAT(gen_params=self.gen_params))
+        self.m = m
+
+        self.log_regs = self.gen_params.isa.reg_cnt
+        self.phys_regs = 2**self.gen_params.phys_regs_bits
+
+        self.to_execute_list = deque()
+        self.expected_entries = [0 for _ in range(self.log_regs)]
+
+        self.gen_input()
+        with self.run_simulation(m) as sim:
+            sim.add_sync_process(self.do_commit)