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Merge branch 'master' into lekcyjna/port-cam
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Lekcyjna committed Mar 17, 2024
2 parents 7a14803 + 1c273ff commit deb7ccc
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6 changes: 3 additions & 3 deletions .github/workflows/benchmark.yml
Original file line number Diff line number Diff line change
Expand Up @@ -38,7 +38,7 @@ jobs:
- name: Synthesize
run: |
. venv/bin/activate
PYTHONHASHSEED=0 ./scripts/synthesize.py --verbose --config ${{ matrix.config }}
PYTHONHASHSEED=0 ./scripts/synthesize.py --verbose --strip-debug --config ${{ matrix.config }}
- name: Print synthesis information
run: cat ./build/top.tim
Expand All @@ -63,7 +63,7 @@ jobs:
build-perf-benchmarks:
name: Build performance benchmarks
runs-on: ubuntu-latest
container: ghcr.io/kuznia-rdzeni/riscv-toolchain:2023.11.19_v
container: ghcr.io/kuznia-rdzeni/riscv-toolchain:2024.03.12
steps:
- name: Checkout
uses: actions/checkout@v3
Expand All @@ -82,7 +82,7 @@ jobs:
run-perf-benchmarks:
name: Run performance benchmarks
runs-on: ubuntu-latest
timeout-minutes: 60
timeout-minutes: 30
container: ghcr.io/kuznia-rdzeni/verilator:v5.008-2023.11.19_v
needs: build-perf-benchmarks
steps:
Expand Down
156 changes: 120 additions & 36 deletions .github/workflows/main.yml
Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ jobs:
python3 -m venv venv
. venv/bin/activate
python3 -m pip install --upgrade pip
python3 -m pip install -r requirements-dev.txt
python3 -m pip install -r requirements.txt
- name: Generate Verilog
run: |
Expand All @@ -40,13 +40,15 @@ jobs:
- uses: actions/upload-artifact@v3
with:
name: "verilog-full-core"
path: core.v
path: |
core.v
core.v.json
build-riscof-tests:
name: Build regression tests (riscv-arch-test)
runs-on: ubuntu-latest
container: ghcr.io/kuznia-rdzeni/riscv-toolchain:2023.11.19_v
container: ghcr.io/kuznia-rdzeni/riscv-toolchain:2024.03.12
timeout-minutes: 10
env:
PYENV_ROOT: "/root/.pyenv"
Expand All @@ -55,35 +57,77 @@ jobs:
defaults:
run:
working-directory: test/external/riscof/

steps:
- name: Checkout
uses: actions/checkout@v3

- name: Setup PATH
- name: Get submodules HEAD hash
working-directory: .
run: |
# ownership workaround
git config --global --add safe.directory /__w/coreblocks/coreblocks
# paths in command are relative!
git submodule > .gitmodules-hash
- name: Cache compiled and reference riscv-arch-test
id: cache-riscv-arch-test
uses: actions/cache@v3
env:
cache-name: cache-riscv-arch-test
with:
path: |
test/external/riscof/riscv-arch-test/**/*.elf
test/external/riscof/riscof_work/**/*.signature
test/external/riscof/**/*Makefile*
key: ${{ env.cache-name }}-${{ runner.os }}-${{ hashFiles(
'**/test/external/riscof/coreblocks/**',
'**/test/external/riscof/spike_simple/**',
'**/test/external/riscof/config.ini',
'**/.gitmodules-hash',
'**/docker/riscv-toolchain.Dockerfile',
'**/.github/workflows/main.yml'
) }}
lookup-only: true

- if: ${{ steps.cache-riscv-arch-test.outputs.cache-hit != 'true' }}
name: Checkout with submodules
uses: actions/checkout@v3
with:
submodules: recursive

- if: ${{ steps.cache-riscv-arch-test.outputs.cache-hit != 'true' }}
name: Setup PATH
run: echo "/.pyenv/bin" >> $GITHUB_PATH

- name: Setup pyenv python
- if: ${{ steps.cache-riscv-arch-test.outputs.cache-hit != 'true' }}
name: Setup pyenv python
run: |
eval "$(pyenv init --path)"
pyenv global 3.6.15
. /venv3.6/bin/activate
- name: Setup arch test suite
- if: ${{ steps.cache-riscv-arch-test.outputs.cache-hit != 'true' }}
name: Setup arch test suite
run: |
. /venv3.6/bin/activate
riscof --verbose info arch-test --clone
riscof testlist --config=config.ini --suite=riscv-arch-test/riscv-test-suite/ --env=riscv-arch-test/riscv-test-suite/env
- name: Build and run tests on reference and generate Makefiles
- if: ${{ steps.cache-riscv-arch-test.outputs.cache-hit != 'true' }}
name: Build and run tests on reference and generate Makefiles
run: |
. /venv3.6/bin/activate
riscof run --config=config.ini --suite=riscv-arch-test/riscv-test-suite/ --env=riscv-arch-test/riscv-test-suite/env
- name: Build tests for Coreblocks
- if: ${{ steps.cache-riscv-arch-test.outputs.cache-hit != 'true' }}
name: Build tests for Coreblocks
run: |
MAKEFILE_PATH=riscof_work/Makefile.build-DUT-coreblocks ../../../ci/riscof_run_makefile.sh
- uses: actions/upload-artifact@v3
- if: ${{ steps.cache-riscv-arch-test.outputs.cache-hit != 'true' }}
name: Upload compiled and reference tests artifact
uses: actions/upload-artifact@v3
with:
name: "riscof-tests"
path: |
Expand All @@ -96,7 +140,7 @@ jobs:
runs-on: ubuntu-latest
container: ghcr.io/kuznia-rdzeni/verilator:v5.008-2023.11.19_v
needs: [ build-riscof-tests, build-core ]
timeout-minutes: 20
timeout-minutes: 30
steps:
- name: Checkout
uses: actions/checkout@v3
Expand All @@ -114,14 +158,35 @@ jobs:
python3 -m pip install -r requirements-dev.txt
- uses: actions/download-artifact@v3
name: Download full verilog core
with:
name: "verilog-full-core"
path: .

- uses: actions/download-artifact@v3
- name: Get submodules HEAD hash
run: |
git config --global --add safe.directory /__w/coreblocks/coreblocks
git submodule > .gitmodules-hash
- uses: actions/cache@v3
name: Download tests from cache
env:
cache-name: cache-riscv-arch-test
with:
name: "riscof-tests"
path: test/external/riscof/
path: |
test/external/riscof/riscv-arch-test/**/*.elf
test/external/riscof/riscof_work/**/*.signature
test/external/riscof/**/*Makefile*
key: ${{ env.cache-name }}-${{ runner.os }}-${{ hashFiles(
'**/test/external/riscof/coreblocks/**',
'**/test/external/riscof/spike_simple/**',
'**/test/external/riscof/config.ini',
'**/.gitmodules-hash',
'**/docker/riscv-toolchain.Dockerfile',
'**/.github/workflows/main.yml'
) }}
fail-on-cache-miss: true

- name: Run tests on Coreblocks
run: |
Expand All @@ -135,14 +200,16 @@ jobs:
build-regression-tests:
name: Build regression tests (riscv-tests)
runs-on: ubuntu-latest
container: ghcr.io/kuznia-rdzeni/riscv-toolchain:2023.11.19_v
outputs:
cache_hit: ${{ steps.cache-regression.outputs.cache-hit }}
container: ghcr.io/kuznia-rdzeni/riscv-toolchain:2024.03.12
timeout-minutes: 10
steps:
- name: Checkout
uses: actions/checkout@v3
with:
submodules: recursive

- name: Get submodules HEAD hash
run: |
git config --global --add safe.directory /__w/coreblocks/coreblocks
git submodule > .gitmodules-hash
- name: Cache regression-tests
id: cache-regression
Expand All @@ -151,15 +218,20 @@ jobs:
cache-name: cache-regression-tests
with:
path: test/external/riscv-tests/test-*

key: ${{ env.cache-name }}-${{ runner.os }}-${{ hashFiles(
'**/test/external/riscv-tests/environment/**',
'**/test/external/riscv-tests/environment/custom/**',
'**/test/external/riscv-tests/Makefile',
'**/.git/modules/test/external/riscv-tests/riscv-tests/HEAD',
'**/docker/riscv-toolchain.Dockerfile'
'**/.gitmodules-hash',
'**/docker/riscv-toolchain.Dockerfile',
'**/.github/workflows/main.yml'
) }}
restore-keys: |
${{ env.cache-name }}-${{ runner.os }}-
lookup-only: true

- if: ${{ steps.cache-regression.outputs.cache-hit != 'true' }}
name: Checkout with submodules
uses: actions/checkout@v3
with:
submodules: recursive

- if: ${{ steps.cache-regression.outputs.cache-hit != 'true' }}
run: cd test/external/riscv-tests && make
Expand All @@ -179,8 +251,6 @@ jobs:
steps:
- name: Checkout
uses: actions/checkout@v3
with:
submodules: recursive

- name: Set up Python
uses: actions/setup-python@v4
Expand All @@ -195,35 +265,46 @@ jobs:
python3 -m pip install -r requirements-dev.txt
- uses: actions/download-artifact@v3
name: Download full verilog core
with:
name: "verilog-full-core"
path: .

- name: Get submodules HEAD hash
run: |
git config --global --add safe.directory /__w/coreblocks/coreblocks
git submodule > .gitmodules-hash
- uses: actions/cache@v3
name: Download tests from cache
env:
cache-name: cache-regression-tests
with:
path: test/external/riscv-tests/test-*
key: ${{ env.cache-name }}-${{ runner.os }}-${{ hashFiles(
'**/test/external/riscv-tests/environment/**',
'**/test/external/riscv-tests/Makefile',
'**/.git/modules/test/external/riscv-tests/riscv-tests/HEAD',
'**/docker/riscv-toolchain.Dockerfile'
) }}
'**/test/external/riscv-tests/environment/custom/**',
'**/test/external/riscv-tests/Makefile',
'**/.gitmodules-hash',
'**/docker/riscv-toolchain.Dockerfile',
'**/.github/workflows/main.yml'
) }}
fail-on-cache-miss: true

- name: Run tests
run: |
. venv/bin/activate
scripts/run_tests.py -a regression
- name: Check for test failure
run: ./scripts/check_test_results.py
- name: Check regression with pysim
run: |
. venv/bin/activate
./scripts/run_tests.py -c 1 -a -b pysim regression
unit-test:
name: Run unit tests
runs-on: ubuntu-latest
timeout-minutes: 10
timeout-minutes: 15
steps:
- name: Checkout
uses: actions/checkout@v3
Expand All @@ -244,11 +325,14 @@ jobs:
sudo apt-get install -y binutils-riscv64-unknown-elf
- name: Run tests
run: ./scripts/run_tests.py --verbose
run: ./scripts/run_tests.py -v

- name: Check traces and profiles
run: ./scripts/run_tests.py -t -p -c 1 TestCore

- name: Check listing tests
run: ./scripts/run_tests.py -l

lint:
name: Check code formatting and typing
runs-on: ubuntu-latest
Expand Down
6 changes: 6 additions & 0 deletions .gitignore
Original file line number Diff line number Diff line change
Expand Up @@ -15,13 +15,19 @@ venv.bak/
# Verilog files
*.v

# Verilog generation debug files
*.v.json

# Waveform dumps
*.vcd
*.gtkw

# Tests outputs
test/__traces__
test/__profiles__/*.json
pytestdebug.log
_coreblocks_regression.lock
_coreblocks_regression.counter

# cocotb build
/test/regression/cocotb/build
Expand Down
3 changes: 3 additions & 0 deletions .gitmodules
Original file line number Diff line number Diff line change
Expand Up @@ -5,3 +5,6 @@
path = test/external/embench/embench-iot
url = https://github.com/embench/embench-iot.git
ignore = dirty
[submodule "test/external/riscof/riscv-arch-test"]
path = test/external/riscof/riscv-arch-test
url = https://github.com/riscv-non-isa/riscv-arch-test.git
4 changes: 2 additions & 2 deletions README.md
Original file line number Diff line number Diff line change
Expand Up @@ -15,14 +15,14 @@ Coreblocks is an experimental, modular out-of-order [RISC-V](https://riscv.org/s

In the future, we would like to achieve the following goals:

* Performace (up to a point, on FPGAs). We would like Coreblocks not to be too sluggish, without compromising the simplicity goal.
* Performance (up to a point, on FPGAs). We would like Coreblocks not to be too sluggish, without compromising the simplicity goal.
We don't wish to compete with high performance cores like [BOOM](https://github.com/riscv-boom/riscv-boom) though.
* Wide(r) RISC-V support. Currently, we are focusing on getting the support for the core RV32I ISA right, but the ambitious long term plan is to be able to run full operating systems (e.g. Linux) on the core.

## State of the project

The core currently supports the full RV32I instruction set and several extensions, including M (multiplication and division) and C (compressed instructions).
Interrupts and exceptions are currently not supported.
Exceptions and some of machine-mode CSRs are supported, the support for interrupts is currently rudimentary and incompatible with the RISC-V spec.
Coreblocks can be used with [LiteX](https://github.com/enjoy-digital/litex) (currently using a [patched version](https://github.com/kuznia-rdzeni/litex/tree/coreblocks)).

The transaction system we use as the foundation for the core is well-tested and usable.
Expand Down
6 changes: 3 additions & 3 deletions constants/ecp5_platforms.py
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@
from itertools import chain
from typing import TypeAlias
from amaranth.build.dsl import Subsignal
from amaranth.vendor.lattice_ecp5 import LatticeECP5Platform
from amaranth.vendor import LatticeECP5Platform
from amaranth.build import Resource, Attrs, Pins, Clock, PinsN

from constants.ecp5_pinout import ecp5_bg756_pins, ecp5_bg756_pclk
Expand Down Expand Up @@ -97,8 +97,8 @@ def make_resources(pins: PinManager) -> list[Resource]:
number,
en=pins.p(),
done=pins.p(),
data_in=pins.p(adapter.data_in.shape().width),
data_out=pins.p(adapter.data_out.shape().width),
data_in=pins.p(adapter.data_in.shape().size),
data_out=pins.p(adapter.data_out.shape().size),
)
]

Expand Down
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