Skip to content

Commit

Permalink
Remove print
Browse files Browse the repository at this point in the history
  • Loading branch information
Jacob Urbanczyk committed Mar 26, 2024
1 parent e7b7e4a commit dc1fd19
Showing 1 changed file with 0 additions and 12 deletions.
12 changes: 0 additions & 12 deletions test/frontend/test_fetch.py
Original file line number Diff line number Diff line change
Expand Up @@ -106,8 +106,6 @@ def add_instr(self, data: int, jumps: bool, jump_offset: int = 0, branch_taken:
}
)

print(f"adding instr pc=0x{self.pc:x} 0x{data:x}, rvc: {rvc}, jumps: {jumps}, next_pc: {next_pc:x}")

instr_pc = self.pc
self.pc = next_pc

Expand Down Expand Up @@ -208,8 +206,6 @@ def load_or_gen_mem(addr):
if req_addr + i in self.memerr:
bad_addr = True

print(f"Cache process request: 0x{req_addr:x} error:{bad_addr}, block={fetch_block:x}")

self.output_q.append({"fetch_block": fetch_block, "error": bad_addr})

@def_method_mock(lambda self: self.icache.issue_req_io, enable=lambda self: len(self.input_q) < 2, sched_prio=1)
Expand All @@ -224,8 +220,6 @@ def fetch_out_check(self):
while self.instr_queue:
instr = self.instr_queue.popleft()

print(f"fetch out {instr['pc']:x}", instr["branch_taken"])

access_fault = instr["pc"] in self.memerr
if not instr["rvc"]:
access_fault |= instr["pc"] + 2 in self.memerr
Expand All @@ -240,18 +234,14 @@ def fetch_out_check(self):
self.assertEqual(v["instr"], instr_data)

if (instr["jumps"] and (instr["branch_taken"] != v["predicted_taken"])) or access_fault:
print("redirecting!!!!", v["predicted_taken"])
yield from self.random_wait(5)
yield from self.fetch_stall_exception.call()
yield from self.random_wait(5)
print("about to clean")

# Empty the pipeline
yield from self.clean_fifo.call_try()
yield

print("cleaned")

resume_pc = instr["next_pc"]
if access_fault:
# Resume from the next fetch block
Expand All @@ -263,8 +253,6 @@ def fetch_out_check(self):
while (yield from self.fetch_resume.call_try(pc=resume_pc, resume_from_exception=1)) is None:
pass

print("resumed")

def run_sim(self):
with self.run_simulation(self.m) as sim:
sim.add_sync_process(self.cache_process)
Expand Down

0 comments on commit dc1fd19

Please sign in to comment.