Merge remote-tracking branch 'origin/master' into tilk/profiles-cocotb

constants/ecp5_platforms.py

@@ -2,7 +2,7 @@
 from itertools import chain
 from typing import TypeAlias
 from amaranth.build.dsl import Subsignal
-from amaranth.vendor.lattice_ecp5 import LatticeECP5Platform
+from amaranth.vendor import LatticeECP5Platform
 from amaranth.build import Resource, Attrs, Pins, Clock, PinsN
 
 from constants.ecp5_pinout import ecp5_bg756_pins, ecp5_bg756_pclk

coreblocks/cache/icache.py

@@ -2,7 +2,7 @@
 import operator
 
 from amaranth import *
-from amaranth.utils import log2_int
+from amaranth.utils import exact_log2
 
 from transactron.core import def_method, Priority, TModule
 from transactron import Method, Transaction
@@ -52,7 +52,7 @@ def _(addr: Value) -> None:
             m.d.sync += req_addr.eq(addr)
             self.bus_master.request_read(
                 m,
-                addr=addr >> log2_int(self.params.word_width_bytes),
+                addr=addr >> exact_log2(self.params.word_width_bytes),
                 sel=C(1).replicate(self.bus_master.params.data_width // self.bus_master.params.granularity),
             )
 
@@ -350,7 +350,7 @@ def elaborate(self, platform):
 
             # We address the data RAM using machine words, so we have to
             # discard a few least significant bits from the address.
-            redundant_offset_bits = log2_int(self.params.word_width_bytes)
+            redundant_offset_bits = exact_log2(self.params.word_width_bytes)
             rd_addr = Cat(self.data_rd_addr.offset, self.data_rd_addr.index)[redundant_offset_bits:]
             wr_addr = Cat(self.data_wr_addr.offset, self.data_wr_addr.index)[redundant_offset_bits:]
 

coreblocks/cache/refiller.py

@@ -1,10 +1,11 @@
+from amaranth import *
 from coreblocks.cache.icache import CacheRefillerInterface
 from coreblocks.params import ICacheLayouts, ICacheParameters
 from coreblocks.peripherals.bus_adapter import BusMasterInterface
 from transactron.core import Transaction
-from transactron.lib import C, Cat, Elaboratable, Forwarder, Method, Signal, TModule, def_method
+from transactron.lib import Forwarder, Method, TModule, def_method
 
-from amaranth.utils import log2_int
+from amaranth.utils import exact_log2
 
 
 __all__ = ["SimpleCommonBusCacheRefiller"]
@@ -62,7 +63,7 @@ def _():
                 address_fwd.write(m, word_counter=next_word_counter, refill_address=refill_address)
 
             return {
-                "addr": Cat(C(0, log2_int(self.params.word_width_bytes)), word_counter, refill_address),
+                "addr": Cat(C(0, exact_log2(self.params.word_width_bytes)), word_counter, refill_address),
                 "data": fetched.data,
                 "error": fetched.err,
                 "last": last,

coreblocks/frontend/fetch.py

@@ -38,9 +38,6 @@ def __init__(self, gen_params: GenParams, icache: CacheInterface, cont: Method)
         # ExceptionCauseRegister uses separate Transaction for it, so performace is not affected.
         self.stall_exception.add_conflict(self.resume, Priority.LEFT)
 
-        # PC of the last fetched instruction. For now only used in tests.
-        self.pc = Signal(self.gen_params.isa.xlen)
-
     def elaborate(self, platform):
         m = TModule()
 
@@ -91,7 +88,6 @@ def stall(exception=False):
                     with m.If(unsafe_instr):
                         stall()
 
-                    m.d.sync += self.pc.eq(target.addr)
                     m.d.comb += instr.eq(res.instr)
 
                 self.cont(m, instr=instr, pc=target.addr, access_fault=fetch_error, rvc=0)
@@ -138,9 +134,6 @@ def __init__(self, gen_params: GenParams, icache: CacheInterface, cont: Method)
 
         self.perf_rvc = HwCounter("frontend.ifu.rvc", "Number of decompressed RVC instructions")
 
-        # PC of the last fetched instruction. For now only used in tests.
-        self.pc = Signal(self.gen_params.isa.xlen)
-
     def elaborate(self, platform) -> TModule:
         m = TModule()
 
@@ -231,7 +224,6 @@ def elaborate(self, platform) -> TModule:
                     m.d.sync += stalled_unsafe.eq(1)
                     m.d.sync += flushing.eq(1)
 
-                m.d.sync += self.pc.eq(current_pc)
                 with m.If(~cache_resp.error):
                     m.d.sync += current_pc.eq(current_pc + Mux(is_rvc, C(2, 3), C(4, 3)))
 

coreblocks/frontend/instr_description.py

@@ -164,20 +164,23 @@ class Encoding:
         Encoding(Opcode.OP, Funct3.MIN, Funct7.MIN),
         Encoding(Opcode.OP, Funct3.MINU, Funct7.MIN),
         Encoding(Opcode.OP, Funct3.ORN, Funct7.ORN),
+        Encoding(Opcode.OP, Funct3.XNOR, Funct7.XNOR),
+    ],
+    OpType.BIT_ROTATION: [
         Encoding(Opcode.OP, Funct3.ROL, Funct7.ROL),
         Encoding(Opcode.OP, Funct3.ROR, Funct7.ROR),
         Encoding(Opcode.OP_IMM, Funct3.ROR, Funct7.ROR),
-        Encoding(Opcode.OP, Funct3.XNOR, Funct7.XNOR),
     ],
     OpType.UNARY_BIT_MANIPULATION_1: [
-        Encoding(Opcode.OP_IMM, Funct3.ORCB, funct12=Funct12.ORCB),
         Encoding(Opcode.OP_IMM, Funct3.REV8, funct12=Funct12.REV8_32),
         Encoding(Opcode.OP_IMM, Funct3.SEXTB, funct12=Funct12.SEXTB),
         Encoding(Opcode.OP, Funct3.ZEXTH, funct12=Funct12.ZEXTH),
     ],
-    # Instructions SEXTH, SEXTHB, CPOP, CLZ and CTZ  cannot be distiguished by their Funct7 code
+    # Instructions SEXTH, SEXTHB, CPOP, CLZ and CTZ cannot be distiguished by their Funct7 code
+    # ORCB is here because of optimization to not lookup Funct7 in UNARY_BIT_MANIPULATION_1
     OpType.UNARY_BIT_MANIPULATION_2: [
         Encoding(Opcode.OP_IMM, Funct3.SEXTH, funct12=Funct12.SEXTH),
+        Encoding(Opcode.OP_IMM, Funct3.ORCB, funct12=Funct12.ORCB),
     ],
     OpType.UNARY_BIT_MANIPULATION_3: [
         Encoding(Opcode.OP_IMM, Funct3.CLZ, funct12=Funct12.CLZ),

coreblocks/fu/alu.py

@@ -82,14 +82,14 @@ def get_instructions(self) -> Sequence[tuple]:
                 (self.Fn.MAXU, OpType.BIT_MANIPULATION, Funct3.MAXU, Funct7.MAX),
                 (self.Fn.MIN, OpType.BIT_MANIPULATION, Funct3.MIN, Funct7.MIN),
                 (self.Fn.MINU, OpType.BIT_MANIPULATION, Funct3.MINU, Funct7.MIN),
-                (self.Fn.ORCB, OpType.UNARY_BIT_MANIPULATION_1, Funct3.ORCB, Funct7.ORCB),
-                (self.Fn.REV8, OpType.UNARY_BIT_MANIPULATION_1, Funct3.REV8, Funct7.REV8),
-                (self.Fn.SEXTB, OpType.UNARY_BIT_MANIPULATION_1, Funct3.SEXTB, Funct7.SEXTB),
-                (self.Fn.ZEXTH, OpType.UNARY_BIT_MANIPULATION_1, Funct3.ZEXTH, Funct7.ZEXTH),
-                (self.Fn.CPOP, OpType.UNARY_BIT_MANIPULATION_5, Funct3.CPOP, Funct7.CPOP),
-                (self.Fn.SEXTH, OpType.UNARY_BIT_MANIPULATION_2, Funct3.SEXTH, Funct7.SEXTH),
-                (self.Fn.CLZ, OpType.UNARY_BIT_MANIPULATION_3, Funct3.CLZ, Funct7.CLZ),
-                (self.Fn.CTZ, OpType.UNARY_BIT_MANIPULATION_4, Funct3.CTZ, Funct7.CTZ),
+                (self.Fn.REV8, OpType.UNARY_BIT_MANIPULATION_1, Funct3.REV8),
+                (self.Fn.SEXTB, OpType.UNARY_BIT_MANIPULATION_1, Funct3.SEXTB),
+                (self.Fn.ZEXTH, OpType.UNARY_BIT_MANIPULATION_1, Funct3.ZEXTH),
+                (self.Fn.ORCB, OpType.UNARY_BIT_MANIPULATION_2, Funct3.ORCB),
+                (self.Fn.SEXTH, OpType.UNARY_BIT_MANIPULATION_2, Funct3.SEXTH),
+                (self.Fn.CLZ, OpType.UNARY_BIT_MANIPULATION_3, Funct3.CLZ),
+                (self.Fn.CTZ, OpType.UNARY_BIT_MANIPULATION_4, Funct3.CTZ),
+                (self.Fn.CPOP, OpType.UNARY_BIT_MANIPULATION_5, Funct3.CPOP),
             ]
             * self.zbb_enable
         )

coreblocks/fu/shift_unit.py

@@ -34,8 +34,8 @@ def get_instructions(self) -> Sequence[tuple]:
             (self.Fn.SRL, OpType.SHIFT, Funct3.SR, Funct7.SL),
             (self.Fn.SRA, OpType.SHIFT, Funct3.SR, Funct7.SA),
         ] + [
-            (self.Fn.ROR, OpType.BIT_MANIPULATION, Funct3.ROR, Funct7.ROR),
-            (self.Fn.ROL, OpType.BIT_MANIPULATION, Funct3.ROL, Funct7.ROL),
+            (self.Fn.ROR, OpType.BIT_ROTATION, Funct3.ROR),
+            (self.Fn.ROL, OpType.BIT_ROTATION, Funct3.ROL),
         ] * self.zbb_enable
 
 

coreblocks/lsu/dummyLsu.py

@@ -73,7 +73,7 @@ def postprocess_load_data(self, m: ModuleLike, funct3: Value, raw_data: Value, a
                     m.d.av_comb += data.eq(tmp.as_signed())
                 with m.Else():
                     m.d.av_comb += data.eq(tmp)
-            with m.Case():
+            with m.Default():
                 m.d.av_comb += data.eq(raw_data)
         return data
 
@@ -84,7 +84,7 @@ def prepare_data_to_save(self, m: ModuleLike, funct3: Value, raw_data: Value, ad
                 m.d.av_comb += data.eq(raw_data[0:8] << (addr[0:2] << 3))
             with m.Case(Funct3.H):
                 m.d.av_comb += data.eq(raw_data[0:16] << (addr[1] << 4))
-            with m.Case():
+            with m.Default():
                 m.d.av_comb += data.eq(raw_data)
         return data
 
@@ -95,7 +95,7 @@ def check_align(self, m: TModule, funct3: Value, addr: Value):
                 m.d.av_comb += aligned.eq(addr[0:2] == 0)
             with m.Case(Funct3.H, Funct3.HU):
                 m.d.av_comb += aligned.eq(addr[0] == 0)
-            with m.Case():
+            with m.Default():
                 m.d.av_comb += aligned.eq(1)
         return aligned
 

coreblocks/params/genparams.py

@@ -1,6 +1,6 @@
 from __future__ import annotations
 
-from amaranth.utils import log2_int
+from amaranth.utils import exact_log2
 
 from .isa import ISA, gen_isa_string
 from .icache_params import ICacheParameters
@@ -36,7 +36,7 @@ def __init__(self, cfg: CoreConfiguration):
 
         bytes_in_word = self.isa.xlen // 8
         self.wb_params = WishboneParameters(
-            data_width=self.isa.xlen, addr_width=self.isa.xlen - log2_int(bytes_in_word)
+            data_width=self.isa.xlen, addr_width=self.isa.xlen - exact_log2(bytes_in_word)
         )
 
         self.icache_params = ICacheParameters(

coreblocks/params/instr.py

@@ -1,6 +1,6 @@
 from abc import abstractmethod, ABC
 
-from amaranth.hdl.ast import ValueCastable
+from amaranth.hdl import ValueCastable
 from amaranth import *
 
 from transactron.utils import ValueLike

coreblocks/params/optypes.py

@@ -34,6 +34,7 @@ class OpType(IntEnum):
     SINGLE_BIT_MANIPULATION = auto()
     ADDRESS_GENERATION = auto()
     BIT_MANIPULATION = auto()
+    BIT_ROTATION = auto()
     UNARY_BIT_MANIPULATION_1 = auto()
     UNARY_BIT_MANIPULATION_2 = auto()
     UNARY_BIT_MANIPULATION_3 = auto()
@@ -88,6 +89,7 @@ class OpType(IntEnum):
     ],
     Extension.ZBB: [
         OpType.BIT_MANIPULATION,
+        OpType.BIT_ROTATION,
         OpType.UNARY_BIT_MANIPULATION_1,
         OpType.UNARY_BIT_MANIPULATION_2,
         OpType.UNARY_BIT_MANIPULATION_3,

requirements.txt

@@ -1,3 +1,3 @@
 amaranth-yosys==0.35.0.0.post81
-git+https://github.com/amaranth-lang/amaranth@94c504afc7d81738ecdc9523a2615ef43ecbf51a
+git+https://github.com/amaranth-lang/amaranth@115954b4d957b4ba642ad056ab1670bf5d185fb6
 dataclasses-json==0.6.3

stubs/amaranth/_toolchain/yosys.pyi

@@ -0,0 +1,144 @@
+"""
+This type stub file was generated by pyright.
+"""
+
+__all__ = ["YosysError", "YosysBinary", "find_yosys"]
+from typing import Optional
+from pathlib import Path
+
+
+class YosysError(Exception):
+    ...
+
+
+class YosysWarning(Warning):
+    ...
+
+
+class YosysBinary:
+    @classmethod
+    def available(cls) -> bool:
+        """Check for Yosys availability.
+
+        Returns
+        -------
+        available : bool
+            ``True`` if Yosys is installed, ``False`` otherwise. Installed binary may still not
+            be runnable, or might be too old to be useful.
+        """
+        ...
+
+    @classmethod
+    def version(cls) -> Optional[tuple[int, int, int]]:
+        """Get Yosys version.
+
+        Returns
+        -------
+        ``None`` if version number could not be determined, or a 3-tuple ``(major, minor, distance)`` if it could.
+
+        major : int
+            Major version.
+        minor : int
+            Minor version.
+        distance : int
+            Distance to last tag per ``git describe``. May not be exact for system Yosys.
+        """
+        ...
+
+    @classmethod
+    def data_dir(cls) -> pathlib.Path:
+        """Get Yosys data directory.
+
+        Returns
+        -------
+        data_dir : pathlib.Path
+            Yosys data directory (also known as "datdir").
+        """
+        ...
+
+    @classmethod
+    def run(cls, args: list[str], stdin: str=...) -> str:
+        """Run Yosys process.
+
+        Parameters
+        ----------
+        args : list of str
+            Arguments, not including the program name.
+        stdin : str
+            Standard input.
+
+        Returns
+        -------
+        stdout : str
+            Standard output.
+
+        Exceptions
+        ----------
+        YosysError
+            Raised if Yosys returns a non-zero code. The exception message is the standard error
+            output.
+        """
+        ...
+
+
+
+class _BuiltinYosys(YosysBinary):
+    YOSYS_PACKAGE = ...
+    @classmethod
+    def available(cls): # -> bool:
+        ...
+
+    @classmethod
+    def version(cls): # -> tuple[int, int, int]:
+        ...
+
+    @classmethod
+    def data_dir(cls): # -> Traversable:
+        ...
+
+    @classmethod
+    def run(cls, args, stdin=..., *, ignore_warnings=..., src_loc_at=...):
+        ...
+
+
+
+class _SystemYosys(YosysBinary):
+    YOSYS_BINARY = ...
+    @classmethod
+    def available(cls): # -> bool:
+        ...
+
+    @classmethod
+    def version(cls): # -> tuple[int, int, int] | None:
+        ...
+
+    @classmethod
+    def data_dir(cls): # -> Path:
+        ...
+
+    @classmethod
+    def run(cls, args, stdin=..., *, ignore_warnings=..., src_loc_at=...):
+        ...
+
+
+
+def find_yosys(requirement):
+    """Find an available Yosys executable of required version.
+
+    Parameters
+    ----------
+    requirement : function
+        Version check. Should return ``True`` if the version is acceptable, ``False`` otherwise.
+
+    Returns
+    -------
+    yosys_binary : subclass of YosysBinary
+        Proxy for running the requested version of Yosys.
+
+    Exceptions
+    ----------
+    YosysError
+        Raised if required Yosys version is not found.
+    """
+    ...
+

stubs/amaranth/_unused.pyi

@@ -0,0 +1,13 @@
+import sys
+import warnings
+
+__all__ = ["UnusedMustUse", "MustUse"]
+
+
+class UnusedMustUse(Warning):
+    pass
+
+
+class MustUse:
+    _MustUse__silence : bool
+    _MustUse__warning : UnusedMustUse

stubs/amaranth/back/__init__.pyi

@@ -0,0 +1,4 @@
+"""
+This type stub file was generated by pyright.
+"""
+