Turns out WishboneInterfaceWrapper is used in weird places

kuznia-rdzeni · Nov 6, 2023 · d6d8362 · d6d8362
1 parent a4e9046
commit d6d8362
Showing 1 changed file with 14 additions and 16 deletions.
diff --git a/test/peripherals/test_wishbone.py b/test/peripherals/test_wishbone.py
@@ -1,6 +1,5 @@
 import random
 from collections import deque
-from unittest import TestCase
 
 from coreblocks.peripherals.wishbone import *
 
@@ -10,9 +9,8 @@
 
 
 class WishboneInterfaceWrapper:
-    def __init__(self, wishbone_record, test_case: TestCase):
+    def __init__(self, wishbone_record):
         self.wb = wishbone_record
-        self.test_case = test_case
 
     def master_set(self, addr, data, we):
         yield self.wb.dat_w.eq(data)
@@ -27,24 +25,24 @@ def master_release(self, release_cyc=1):
             yield self.wb.cyc.eq(0)
 
     def master_verify(self, exp_data=0):
-        self.test_case.assertTrue((yield self.wb.ack))
-        self.test_case.assertEqual((yield self.wb.dat_r), exp_data)
+        assert (yield self.wb.ack)
+        assert (yield self.wb.dat_r) == exp_data
 
     def slave_wait(self):
         while not ((yield self.wb.stb) and (yield self.wb.cyc)):
             yield
 
     def slave_verify(self, exp_addr, exp_data, exp_we, exp_sel=0):
-        self.test_case.assertTrue((yield self.wb.stb) and (yield self.wb.cyc))
+        assert (yield self.wb.stb) and (yield self.wb.cyc)
 
-        self.test_case.assertEqual((yield self.wb.adr), exp_addr)
-        self.test_case.assertEqual((yield self.wb.we), exp_we)
-        self.test_case.assertEqual((yield self.wb.sel), exp_sel)
+        assert (yield self.wb.adr) == exp_addr
+        assert (yield self.wb.we) == exp_we
+        assert (yield self.wb.sel) == exp_sel
         if exp_we:
-            self.test_case.assertEqual((yield self.wb.dat_w), exp_data)
+            assert (yield self.wb.dat_w) == exp_data
 
     def slave_respond(self, data, ack=1, err=0, rty=0):
-        self.test_case.assertTrue((yield self.wb.stb) and (yield self.wb.cyc))
+        assert (yield self.wb.stb) and (yield self.wb.cyc)
 
         yield self.wb.dat_r.eq(data)
         yield self.wb.ack.eq(ack)
@@ -105,7 +103,7 @@ def result_process():
             self.assertTrue(resp["err"])
 
         def slave():
-            wwb = WishboneInterfaceWrapper(twbm.wbm.wbMaster, self)
+            wwb = WishboneInterfaceWrapper(twbm.wbm.wbMaster)
 
             yield from wwb.slave_wait()
             yield from wwb.slave_verify(2, 0, 0, 1)
@@ -140,9 +138,9 @@ def slave():
 
 class TestWishboneMuxer(TestCaseWithSimulator):
     def test_manual(self):
-        wb_master = WishboneInterfaceWrapper(Record(WishboneLayout(WishboneParameters()).wb_layout), self)
+        wb_master = WishboneInterfaceWrapper(Record(WishboneLayout(WishboneParameters()).wb_layout))
         num_slaves = 4
-        slaves = [WishboneInterfaceWrapper(Record.like(wb_master.wb, name=f"sl{i}"), self) for i in range(num_slaves)]
+        slaves = [WishboneInterfaceWrapper(Record.like(wb_master.wb, name=f"sl{i}")) for i in range(num_slaves)]
         mux = WishboneMuxer(wb_master.wb, [s.wb for s in slaves], Signal(num_slaves))
 
         def process():
@@ -181,8 +179,8 @@ def process():
 
 class TestWishboneAribiter(TestCaseWithSimulator):
     def test_manual(self):
-        slave = WishboneInterfaceWrapper(Record(WishboneLayout(WishboneParameters()).wb_layout), self)
-        masters = [WishboneInterfaceWrapper(Record.like(slave.wb, name=f"mst{i}"), self) for i in range(2)]
+        slave = WishboneInterfaceWrapper(Record(WishboneLayout(WishboneParameters()).wb_layout))
+        masters = [WishboneInterfaceWrapper(Record.like(slave.wb, name=f"mst{i}")) for i in range(2)]
         arb = WishboneArbiter(slave.wb, [m.wb for m in masters])
 
         def process():