Workaround

test/regression/memory.py

@@ -98,7 +98,7 @@ def write(self, req: WriteRequest) -> WriteReply:
 
 
 class CoreMemoryModel:
-    def __init__(self, segments: list[MemorySegment], fail_on_undefined=False):
+    def __init__(self, segments: list[MemorySegment], fail_on_undefined=True):
         self.segments = segments
         self.fail_on_undefined = fail_on_undefined
 
@@ -166,17 +166,18 @@ def load_segment(segment: Segment, *, disable_write_protection: bool = False) ->
         # align instruction section to full icache lines
         align_bits = config.icache_block_size_bits
         # workaround for fetching/stalling issue
-        align_bits += 1
+        extend_end = 2**config.icache_block_size_bits
     else:
         align_bits = 0
+        extend_end = 0
 
     align_data_front = seg_start - align_down_to_power_of_two(seg_start, align_bits)
-    align_data_back = align_to_power_of_two(seg_end, align_bits) - seg_end
+    align_data_back = align_to_power_of_two(seg_end, align_bits) - seg_end + extend_end
 
     data = b"\x00" * align_data_front + data + b"\x00" * align_data_back
 
     seg_start = align_down_to_power_of_two(seg_start, align_bits)
-    seg_end = align_to_power_of_two(seg_end, align_bits)
+    seg_end = align_to_power_of_two(seg_end, align_bits) + extend_end
 
     return RandomAccessMemory(range(seg_start, seg_end), flags, data)