Renamings

test/backend/test_annoucement.py

@@ -9,7 +9,7 @@
 from coreblocks.interface.layouts import *
 from coreblocks.params import GenParams
 from coreblocks.params.configurations import test_core_config
-from transactron.testing import TestCaseWithSimulator, AsyncTestbenchIO
+from transactron.testing import TestCaseWithSimulator, TestbenchIO
 
 
 class BackendTestCircuit(Elaboratable):
@@ -38,7 +38,7 @@ def elaborate(self, platform):
             get_results.append(fifo.read)
             m.submodules[f"fu_fifo_{i}"] = fifo
 
-            fifo_in = AsyncTestbenchIO(AdapterTrans(fifo.write))
+            fifo_in = TestbenchIO(AdapterTrans(fifo.write))
             m.submodules[f"fu_fifo_{i}_in"] = fifo_in
             self.fu_fifo_ins.append(fifo_in)
 
@@ -50,11 +50,11 @@ def elaborate(self, platform):
         )
 
         # Create stubs for interfaces used by result announcement
-        self.rs_announce_val_tbio = AsyncTestbenchIO(Adapter(i=self.lay_rs_write, o=self.lay_rs_write))
+        self.rs_announce_val_tbio = TestbenchIO(Adapter(i=self.lay_rs_write, o=self.lay_rs_write))
         m.submodules.rs_announce_val_tbio = self.rs_announce_val_tbio
-        self.rf_announce_val_tbio = AsyncTestbenchIO(Adapter(i=self.lay_rf_write, o=self.lay_rf_write))
+        self.rf_announce_val_tbio = TestbenchIO(Adapter(i=self.lay_rf_write, o=self.lay_rf_write))
         m.submodules.rf_announce_val_tbio = self.rf_announce_val_tbio
-        self.rob_mark_done_tbio = AsyncTestbenchIO(Adapter(i=self.lay_rob_mark_done, o=self.lay_rob_mark_done))
+        self.rob_mark_done_tbio = TestbenchIO(Adapter(i=self.lay_rob_mark_done, o=self.lay_rob_mark_done))
         m.submodules.rob_mark_done_tbio = self.rob_mark_done_tbio
 
         # Create result announcement
@@ -108,9 +108,9 @@ def generate_producer(self, i: int):
         async def producer(sim: TestbenchContext):
             inputs = self.fu_inputs[i]
             for rob_id, result, rp_dst in inputs:
-                io: AsyncTestbenchIO = self.m.fu_fifo_ins[i]
+                io: TestbenchIO = self.m.fu_fifo_ins[i]
                 io.call_init(sim, rob_id=rob_id, result=result, rp_dst=rp_dst)
-                await self.async_random_wait(sim, self.max_wait)
+                await self.random_wait(sim, self.max_wait)
             self.producer_end[i] = True
 
         return producer
@@ -146,7 +146,7 @@ async def consumer(self, sim: TestbenchContext):
                 del self.expected_output[t]
             else:
                 self.expected_output[t] -= 1
-            await self.async_random_wait(sim, self.max_wait)
+            await self.random_wait(sim, self.max_wait)
 
     def test_one_out(self):
         self.fu_count = 1

test/backend/test_retirement.py

@@ -12,6 +12,7 @@
 from coreblocks.params import GenParams
 from coreblocks.interface.layouts import ROBLayouts, RFLayouts, SchedulerLayouts
 from coreblocks.params.configurations import test_core_config
+from transactron.lib.adapters import AdapterTrans
 
 from transactron.testing import *
 from collections import deque
@@ -39,28 +40,28 @@ def elaborate(self, platform):
             scheduler_layouts.free_rf_layout, 2**self.gen_params.phys_regs_bits
         )
 
-        m.submodules.mock_rob_peek = self.mock_rob_peek = AsyncTestbenchIO(
+        m.submodules.mock_rob_peek = self.mock_rob_peek = TestbenchIO(
             Adapter(o=rob_layouts.peek_layout, nonexclusive=True)
         )
 
-        m.submodules.mock_rob_retire = self.mock_rob_retire = AsyncTestbenchIO(Adapter())
+        m.submodules.mock_rob_retire = self.mock_rob_retire = TestbenchIO(Adapter())
 
-        m.submodules.mock_rf_free = self.mock_rf_free = AsyncTestbenchIO(Adapter(i=rf_layouts.rf_free))
+        m.submodules.mock_rf_free = self.mock_rf_free = TestbenchIO(Adapter(i=rf_layouts.rf_free))
 
-        m.submodules.mock_exception_cause = self.mock_exception_cause = AsyncTestbenchIO(
+        m.submodules.mock_exception_cause = self.mock_exception_cause = TestbenchIO(
             Adapter(o=exception_layouts.get, nonexclusive=True)
         )
-        m.submodules.mock_exception_clear = self.mock_exception_clear = AsyncTestbenchIO(Adapter())
+        m.submodules.mock_exception_clear = self.mock_exception_clear = TestbenchIO(Adapter())
 
         m.submodules.generic_csr = self.generic_csr = GenericCSRRegisters(self.gen_params)
         DependencyContext.get().add_dependency(CSRInstancesKey(), self.generic_csr)
 
-        m.submodules.mock_fetch_continue = self.mock_fetch_continue = AsyncTestbenchIO(Adapter(i=fetch_layouts.resume))
-        m.submodules.mock_instr_decrement = self.mock_instr_decrement = AsyncTestbenchIO(
+        m.submodules.mock_fetch_continue = self.mock_fetch_continue = TestbenchIO(Adapter(i=fetch_layouts.resume))
+        m.submodules.mock_instr_decrement = self.mock_instr_decrement = TestbenchIO(
             Adapter(o=core_instr_counter_layouts.decrement)
         )
-        m.submodules.mock_trap_entry = self.mock_trap_entry = AsyncTestbenchIO(Adapter())
-        m.submodules.mock_async_interrupt_cause = self.mock_async_interrupt_cause = AsyncTestbenchIO(
+        m.submodules.mock_trap_entry = self.mock_trap_entry = TestbenchIO(Adapter())
+        m.submodules.mock_async_interrupt_cause = self.mock_async_interrupt_cause = TestbenchIO(
             Adapter(o=interrupt_controller_layouts.interrupt_cause)
         )
 
@@ -81,10 +82,10 @@ def elaborate(self, platform):
             async_interrupt_cause=self.mock_async_interrupt_cause.adapter.iface,
         )
 
-        m.submodules.free_rf_fifo_adapter = self.free_rf_adapter = AsyncTestbenchIO(AdapterTrans(self.free_rf.read))
+        m.submodules.free_rf_fifo_adapter = self.free_rf_adapter = TestbenchIO(AdapterTrans(self.free_rf.read))
 
         precommit = DependencyContext.get().get_dependency(InstructionPrecommitKey())
-        m.submodules.precommit_adapter = self.precommit_adapter = AsyncTestbenchIO(AdapterTrans(precommit))
+        m.submodules.precommit_adapter = self.precommit_adapter = TestbenchIO(AdapterTrans(precommit))
 
         return m
 

test/cache/test_icache.py

@@ -16,7 +16,7 @@
 from coreblocks.params.configurations import test_core_config
 from coreblocks.cache.refiller import SimpleCommonBusCacheRefiller
 
-from transactron.testing import TestCaseWithSimulator, AsyncTestbenchIO, async_def_method_mock
+from transactron.testing import TestCaseWithSimulator, TestbenchIO, async_def_method_mock
 from transactron.testing.functions import MethodData
 from transactron.testing.sugar import MethodMock
 from transactron.testing.testbenchio import CallTrigger
@@ -42,8 +42,8 @@ def elaborate(self, platform):
             self.gen_params.get(ICacheLayouts), self.cp, self.bus_master_adapter
         )
 
-        self.start_refill = AsyncTestbenchIO(AdapterTrans(self.refiller.start_refill))
-        self.accept_refill = AsyncTestbenchIO(AdapterTrans(self.refiller.accept_refill))
+        self.start_refill = TestbenchIO(AdapterTrans(self.refiller.start_refill))
+        self.accept_refill = TestbenchIO(AdapterTrans(self.refiller.accept_refill))
 
         m.submodules.wb_master = self.wb_master
         m.submodules.bus_master_adapter = self.bus_master_adapter
@@ -109,7 +109,7 @@ async def wishbone_slave(self, sim: TestbenchContext):
             # Wishbone is addressing words, so we need to shift it a bit to get the real address.
             addr = adr << exact_log2(self.cp.word_width_bytes)
 
-            await self.async_random_wait_geom(sim, 0.5)
+            await self.random_wait_geom(sim, 0.5)
 
             err = 1 if addr in self.bad_addresses else 0
 
@@ -169,8 +169,8 @@ def elaborate(self, platform):
         m.submodules.bypass = self.bypass = ICacheBypass(
             self.gen_params.get(ICacheLayouts), self.cp, self.bus_master_adapter
         )
-        m.submodules.issue_req = self.issue_req = AsyncTestbenchIO(AdapterTrans(self.bypass.issue_req))
-        m.submodules.accept_res = self.accept_res = AsyncTestbenchIO(AdapterTrans(self.bypass.accept_res))
+        m.submodules.issue_req = self.issue_req = TestbenchIO(AdapterTrans(self.bypass.issue_req))
+        m.submodules.accept_res = self.accept_res = TestbenchIO(AdapterTrans(self.bypass.accept_res))
 
         self.wb_ctrl = WishboneInterfaceWrapper(self.wb_master.wb_master)
 
@@ -225,7 +225,7 @@ async def wishbone_slave(self, sim: TestbenchContext):
             # Wishbone is addressing words, so we need to shift it a bit to get the real address.
             addr = adr << exact_log2(self.cp.word_width_bytes)
 
-            await self.async_random_wait_geom(sim, 0.5)
+            await self.random_wait_geom(sim, 0.5)
 
             err = 1 if addr in self.bad_addrs else 0
 
@@ -240,7 +240,7 @@ async def user_process(self, sim: TestbenchContext):
             req_addr = self.requests.popleft() & ~(self.cp.fetch_block_bytes - 1)
             await self.m.issue_req.call(sim, addr=req_addr)
 
-            await self.async_random_wait_geom(sim, 0.5)
+            await self.random_wait_geom(sim, 0.5)
 
             ret = await self.m.accept_res.call(sim)
 
@@ -254,7 +254,7 @@ async def user_process(self, sim: TestbenchContext):
                     data |= self.mem[req_addr + 4] << 32
                 assert ret["fetch_block"] == data
 
-            await self.async_random_wait_geom(sim, 0.5)
+            await self.random_wait_geom(sim, 0.5)
 
     def test(self):
         with self.run_simulation(self.m) as sim:
@@ -266,8 +266,8 @@ class MockedCacheRefiller(Elaboratable, CacheRefillerInterface):
     def __init__(self, gen_params: GenParams):
         layouts = gen_params.get(ICacheLayouts)
 
-        self.start_refill_mock = AsyncTestbenchIO(Adapter(i=layouts.start_refill))
-        self.accept_refill_mock = AsyncTestbenchIO(Adapter(o=layouts.accept_refill))
+        self.start_refill_mock = TestbenchIO(Adapter(i=layouts.start_refill))
+        self.accept_refill_mock = TestbenchIO(Adapter(o=layouts.accept_refill))
 
         self.start_refill = self.start_refill_mock.adapter.iface
         self.accept_refill = self.accept_refill_mock.adapter.iface
@@ -291,9 +291,9 @@ def elaborate(self, platform):
 
         m.submodules.refiller = self.refiller = MockedCacheRefiller(self.gen_params)
         m.submodules.cache = self.cache = ICache(self.gen_params.get(ICacheLayouts), self.cp, self.refiller)
-        m.submodules.issue_req = self.issue_req = AsyncTestbenchIO(AdapterTrans(self.cache.issue_req))
-        m.submodules.accept_res = self.accept_res = AsyncTestbenchIO(AdapterTrans(self.cache.accept_res))
-        m.submodules.flush_cache = self.flush_cache = AsyncTestbenchIO(AdapterTrans(self.cache.flush))
+        m.submodules.issue_req = self.issue_req = TestbenchIO(AdapterTrans(self.cache.issue_req))
+        m.submodules.accept_res = self.accept_res = TestbenchIO(AdapterTrans(self.cache.accept_res))
+        m.submodules.flush_cache = self.flush_cache = TestbenchIO(AdapterTrans(self.cache.flush))
 
         return m
 
@@ -491,7 +491,7 @@ async def cache_process(sim: TestbenchContext):
                 await self.call_cache(sim, addr)
                 self.expect_refill(addr)
 
-            await self.async_tick(sim, 4)
+            await self.tick(sim, 4)
 
             # Create a stream of requests to ensure the pipeline is working
             self.m.accept_res.enable(sim)
@@ -508,14 +508,14 @@ async def cache_process(sim: TestbenchContext):
 
             self.m.accept_res.disable(sim)
 
-            await self.async_tick(sim, 4)
+            await self.tick(sim, 4)
 
             # Check how the cache handles queuing the requests
             await self.send_req(sim, addr=0x00010000 + 3 * self.cp.line_size_bytes)
             await self.send_req(sim, addr=0x00010004)
 
             # Wait a few cycles. There are two requests queued
-            await self.async_tick(sim, 4)
+            await self.tick(sim, 4)
 
             self.m.accept_res.enable(sim)
             await self.expect_resp(
@@ -531,7 +531,7 @@ async def cache_process(sim: TestbenchContext):
 
             self.m.accept_res.disable(sim)
 
-            await self.async_tick(sim, 4)
+            await self.tick(sim, 4)
 
             # Schedule two requests, the first one causing a cache miss
             await self.send_req(sim, addr=0x00020000)
@@ -545,7 +545,7 @@ async def cache_process(sim: TestbenchContext):
             )
             self.m.accept_res.disable(sim)
 
-            await self.async_tick(sim, 2)
+            await self.tick(sim, 2)
 
             # Schedule two requests, the second one causing a cache miss
             await self.send_req(sim, addr=0x00020004)
@@ -559,7 +559,7 @@ async def cache_process(sim: TestbenchContext):
             await self.expect_resp(sim, wait=True)
             self.m.accept_res.disable(sim)
 
-            await self.async_tick(sim, 2)
+            await self.tick(sim, 2)
 
             # Schedule two requests, both causing a cache miss
             await self.send_req(sim, addr=0x00040000)
@@ -686,21 +686,21 @@ async def cache_process(sim: TestbenchContext):
             await self.expect_resp(sim, wait=True)
             self.m.accept_res.disable(sim)
 
-            await self.async_tick(sim, 3)
+            await self.tick(sim, 3)
 
             # Schedule two requests, the second one causing an error
             await self.send_req(sim, addr=0x00021004)
             await self.send_req(sim, addr=0x00030000)
 
-            await self.async_tick(sim, 10)
+            await self.tick(sim, 10)
 
             self.m.accept_res.enable(sim)
 
             await self.expect_resp(sim, wait=True)
             await self.expect_resp(sim, wait=True)
             self.m.accept_res.disable(sim)
 
-            await self.async_tick(sim, 3)
+            await self.tick(sim, 3)
 
             # Schedule two requests, both causing an error
             await self.send_req(sim, addr=0x00020000)
@@ -716,15 +716,15 @@ async def cache_process(sim: TestbenchContext):
             await self.send_req(sim, addr=0x00021004)
             await self.send_req(sim, addr=0x00030000)
 
-            await self.async_tick(sim, 10)
+            await self.tick(sim, 10)
 
             # Accept the first response
             self.m.accept_res.enable(sim)
             await self.expect_resp(sim, wait=True)
 
             # Wait before accepting the second response
             self.m.accept_res.disable(sim)
-            await self.async_tick(sim, 10)
+            await self.tick(sim, 10)
             self.m.accept_res.enable(sim)
             await self.expect_resp(sim, wait=True)
 
@@ -747,24 +747,24 @@ def test_random(self):
 
         async def refiller_ctrl(sim: TestbenchContext):
             while True:
-                await self.async_random_wait_geom(sim, 0.4)
+                await self.random_wait_geom(sim, 0.4)
                 self.accept_refill_request = False
 
-                await self.async_random_wait_geom(sim, 0.7)
+                await self.random_wait_geom(sim, 0.7)
                 self.accept_refill_request = True
 
         async def sender(sim: TestbenchContext):
             for _ in range(iterations):
                 await self.send_req(sim, random.randrange(0, max_addr, 4))
-                await self.async_random_wait_geom(sim, 0.5)
+                await self.random_wait_geom(sim, 0.5)
 
         async def receiver(sim: TestbenchContext):
             for _ in range(iterations):
                 while len(self.issued_requests) == 0:
                     await sim.tick()
 
                 self.assert_resp(await self.m.accept_res.call(sim))
-                await self.async_random_wait_geom(sim, 0.2)
+                await self.random_wait_geom(sim, 0.2)
 
         with self.run_simulation(self.m) as sim:
             sim.add_testbench(sender)

test/core_structs/test_rat.py

@@ -40,7 +40,7 @@ def test_single(self):
         self.rand = Random(0)
         self.test_steps = 2000
         self.gen_params = GenParams(test_core_config.replace(phys_regs_bits=5, rob_entries_bits=6))
-        m = SimpleTestCircuit(FRAT(gen_params=self.gen_params), async_tb=True)
+        m = SimpleTestCircuit(FRAT(gen_params=self.gen_params))
         self.m = m
 
         self.log_regs = self.gen_params.isa.reg_cnt
@@ -80,7 +80,7 @@ def test_single(self):
         self.rand = Random(0)
         self.test_steps = 2000
         self.gen_params = GenParams(test_core_config.replace(phys_regs_bits=5, rob_entries_bits=6))
-        m = SimpleTestCircuit(RRAT(gen_params=self.gen_params), async_tb=True)
+        m = SimpleTestCircuit(RRAT(gen_params=self.gen_params))
         self.m = m
 
         self.log_regs = self.gen_params.isa.reg_cnt

test/core_structs/test_reorder_buffer.py

@@ -17,7 +17,7 @@ async def gen_input(self, sim: TestbenchContext):
             while self.regs_left_queue.empty():
                 await sim.tick()
 
-            await self.async_random_wait_geom(sim, 0.5)  # to slow down puts
+            await self.random_wait_geom(sim, 0.5)  # to slow down puts
             log_reg = self.rand.randint(0, self.log_regs - 1)
             phys_reg = self.regs_left_queue.get()
             regs = {"rl_dst": log_reg, "rp_dst": phys_reg}
@@ -27,7 +27,7 @@ async def gen_input(self, sim: TestbenchContext):
 
     async def do_updates(self, sim: TestbenchContext):
         while True:
-            await self.async_random_wait_geom(sim, 0.5)  # to slow down execution
+            await self.random_wait_geom(sim, 0.5)  # to slow down execution
             if len(self.to_execute_list) == 0:
                 await sim.tick()
             else:
@@ -64,7 +64,7 @@ def test_single(self):
         self.gen_params = GenParams(
             test_core_config.replace(phys_regs_bits=5, rob_entries_bits=6)
         )  # smaller size means better coverage
-        m = SimpleTestCircuit(ReorderBuffer(self.gen_params), async_tb=True)
+        m = SimpleTestCircuit(ReorderBuffer(self.gen_params))
         self.m = m
 
         self.regs_left_queue = Queue()
@@ -115,7 +115,7 @@ def test_single(self):
 
         self.gen_params = GenParams(test_core_config)
         self.test_steps = 2**self.gen_params.rob_entries_bits
-        m = SimpleTestCircuit(ReorderBuffer(self.gen_params), async_tb=True)
+        m = SimpleTestCircuit(ReorderBuffer(self.gen_params))
         self.m = m
         self.to_execute_list = []