Merge branch 'master' into piotro/ci-optimize-submodule-downloads

coreblocks/cache/icache.py

@@ -2,6 +2,7 @@
 import operator
 
 from amaranth import *
+from amaranth.lib.data import View
 from amaranth.utils import exact_log2
 
 from transactron.core import def_method, Priority, TModule
@@ -12,6 +13,7 @@
 from coreblocks.peripherals.bus_adapter import BusMasterInterface
 
 from coreblocks.cache.iface import CacheInterface, CacheRefillerInterface
+from transactron.utils.transactron_helpers import make_layout
 
 __all__ = [
     "ICache",
@@ -109,11 +111,11 @@ def __init__(self, layouts: ICacheLayouts, params: ICacheParameters, refiller: C
         self.flush = Method()
         self.flush.add_conflict(self.issue_req, Priority.LEFT)
 
-        self.addr_layout = [
+        self.addr_layout = make_layout(
             ("offset", self.params.offset_bits),
             ("index", self.params.index_bits),
             ("tag", self.params.tag_bits),
-        ]
+        )
 
         self.perf_loads = HwCounter("frontend.icache.loads", "Number of requests to the L1 Instruction Cache")
         self.perf_hits = HwCounter("frontend.icache.hits")
@@ -131,7 +133,7 @@ def deserialize_addr(self, raw_addr: Value) -> dict[str, Value]:
             "tag": raw_addr[-self.params.tag_bits :],
         }
 
-    def serialize_addr(self, addr: Record) -> Value:
+    def serialize_addr(self, addr: View) -> Value:
         return Cat(addr.offset, addr.index, addr.tag)
 
     def elaborate(self, platform):
@@ -186,7 +188,7 @@ def elaborate(self, platform):
 
         # Fast path - read requests
         request_valid = self.req_fifo.read.ready
-        request_addr = Record(self.addr_layout)
+        request_addr = Signal(self.addr_layout)
 
         tag_hit = [tag_data.valid & (tag_data.tag == request_addr.tag) for tag_data in self.mem.tag_rd_data]
         tag_hit_any = reduce(operator.or_, tag_hit)
@@ -195,7 +197,7 @@ def elaborate(self, platform):
         for i in OneHotSwitchDynamic(m, Cat(tag_hit)):
             m.d.comb += mem_out.eq(self.mem.data_rd_data[i])
 
-        instr_out = extract_instr_from_word(m, self.params, mem_out, request_addr[:])
+        instr_out = extract_instr_from_word(m, self.params, mem_out, Value.cast(request_addr))
 
         refill_error_saved = Signal()
         m.d.comb += needs_refill.eq(request_valid & ~tag_hit_any & ~refill_error_saved)
@@ -214,7 +216,7 @@ def _():
             self.req_latency.stop(m)
             return self.res_fwd.read(m)
 
-        mem_read_addr = Record(self.addr_layout)
+        mem_read_addr = Signal(self.addr_layout)
         m.d.comb += assign(mem_read_addr, request_addr)
 
         @def_method(m, self.issue_req, ready=accepting_requests)
@@ -304,21 +306,21 @@ class ICacheMemory(Elaboratable):
     def __init__(self, params: ICacheParameters) -> None:
         self.params = params
 
-        self.tag_data_layout = [("valid", 1), ("tag", self.params.tag_bits)]
+        self.tag_data_layout = make_layout(("valid", 1), ("tag", self.params.tag_bits))
 
         self.way_wr_en = Signal(self.params.num_of_ways)
 
         self.tag_rd_index = Signal(self.params.index_bits)
-        self.tag_rd_data = Array([Record(self.tag_data_layout) for _ in range(self.params.num_of_ways)])
+        self.tag_rd_data = Array([Signal(self.tag_data_layout) for _ in range(self.params.num_of_ways)])
         self.tag_wr_index = Signal(self.params.index_bits)
         self.tag_wr_en = Signal()
-        self.tag_wr_data = Record(self.tag_data_layout)
+        self.tag_wr_data = Signal(self.tag_data_layout)
 
-        self.data_addr_layout = [("index", self.params.index_bits), ("offset", self.params.offset_bits)]
+        self.data_addr_layout = make_layout(("index", self.params.index_bits), ("offset", self.params.offset_bits))
 
-        self.data_rd_addr = Record(self.data_addr_layout)
+        self.data_rd_addr = Signal(self.data_addr_layout)
         self.data_rd_data = Array([Signal(self.params.word_width) for _ in range(self.params.num_of_ways)])
-        self.data_wr_addr = Record(self.data_addr_layout)
+        self.data_wr_addr = Signal(self.data_addr_layout)
         self.data_wr_en = Signal()
         self.data_wr_data = Signal(self.params.word_width)
 
@@ -328,7 +330,7 @@ def elaborate(self, platform):
         for i in range(self.params.num_of_ways):
             way_wr = self.way_wr_en[i]
 
-            tag_mem = Memory(width=len(self.tag_wr_data), depth=self.params.num_of_sets)
+            tag_mem = Memory(width=len(Value.cast(self.tag_wr_data)), depth=self.params.num_of_sets)
             tag_mem_rp = tag_mem.read_port()
             tag_mem_wp = tag_mem.write_port()
             m.submodules[f"tag_mem_{i}_rp"] = tag_mem_rp

coreblocks/core.py

@@ -1,4 +1,5 @@
 from amaranth import *
+from amaranth.lib.wiring import flipped, connect
 
 from transactron.utils.dependencies import DependencyManager, DependencyContext
 from coreblocks.stages.func_blocks_unifier import FuncBlocksUnifier
@@ -27,7 +28,7 @@
 from coreblocks.stages.retirement import Retirement
 from coreblocks.cache.icache import ICache, ICacheBypass
 from coreblocks.peripherals.bus_adapter import WishboneMasterAdapter
-from coreblocks.peripherals.wishbone import WishboneMaster, WishboneBus
+from coreblocks.peripherals.wishbone import WishboneMaster, WishboneInterface
 from coreblocks.cache.refiller import SimpleCommonBusCacheRefiller
 from coreblocks.frontend.fetch import Fetch, UnalignedFetch
 from transactron.lib.transformers import MethodMap, MethodProduct
@@ -38,7 +39,7 @@
 
 
 class Core(Elaboratable):
-    def __init__(self, *, gen_params: GenParams, wb_instr_bus: WishboneBus, wb_data_bus: WishboneBus):
+    def __init__(self, *, gen_params: GenParams, wb_instr_bus: WishboneInterface, wb_data_bus: WishboneInterface):
         self.gen_params = gen_params
 
         dep_manager = DependencyContext.get()
@@ -117,8 +118,8 @@ def __init__(self, *, gen_params: GenParams, wb_instr_bus: WishboneBus, wb_data_
     def elaborate(self, platform):
         m = TModule()
 
-        m.d.comb += self.wb_master_instr.wb_master.connect(self.wb_instr_bus)
-        m.d.comb += self.wb_master_data.wb_master.connect(self.wb_data_bus)
+        connect(m, flipped(self.wb_instr_bus), self.wb_master_instr.wb_master)
+        connect(m, flipped(self.wb_data_bus), self.wb_master_data.wb_master)
 
         m.submodules.wb_master_instr = self.wb_master_instr
         m.submodules.wb_master_data = self.wb_master_data

coreblocks/fu/div_unit.py

@@ -3,6 +3,7 @@
 from collections.abc import Sequence
 
 from amaranth import *
+from amaranth.lib import data
 
 from coreblocks.params.fu_params import FunctionalComponentParams
 from coreblocks.params import Funct3, GenParams, FuncUnitLayouts, OpType
@@ -33,7 +34,7 @@ def get_instructions(self) -> Sequence[tuple]:
         ]
 
 
-def get_input(arg: Record) -> tuple[Value, Value]:
+def get_input(arg: data.View) -> tuple[Value, Value]:
     return arg.s1_val, Mux(arg.imm, arg.imm, arg.s2_val)
 
 

coreblocks/fu/fu_decoder.py

@@ -15,7 +15,7 @@ class Decoder(Elaboratable):
     Attributes
     ----------
     decode_fn: Signal
-    exec_fn: Record
+    exec_fn: View
     """
 
     def __init__(self, gen_params: GenParams, decode_fn: Type[IntFlag], ops: Sequence[tuple], check_optype: bool):

coreblocks/lsu/pma.py

@@ -2,6 +2,7 @@
 from functools import reduce
 from operator import or_
 from amaranth import *
+from amaranth.lib import data
 
 from coreblocks.params import *
 from transactron.utils import HasElaborate
@@ -29,6 +30,11 @@ class PMARegion:
     mmio: bool = False
 
 
+class PMALayout(data.StructLayout):
+    def __init__(self):
+        super().__init__({"mmio": unsigned(1)})
+
+
 class PMAChecker(Elaboratable):
     """
     Implementation of physical memory attributes checker. It may or may not be a part of LSU.
@@ -38,21 +44,20 @@ class PMAChecker(Elaboratable):
     ----------
     addr : Signal
         Memory address, for which PMAs are requested.
-    result : Record
+    result : View
         PMAs for given address.
     """
 
     def __init__(self, gen_params: GenParams) -> None:
         # poor man's interval list
         self.segments = gen_params.pma
-        self.attr_layout = gen_params.get(PMALayouts).pma_attrs_layout
-        self.result = Record(self.attr_layout)
+        self.result = Signal(PMALayout())
         self.addr = Signal(gen_params.isa.xlen)
 
     def elaborate(self, platform) -> HasElaborate:
         m = TModule()
 
-        outputs = [Record(self.attr_layout) for _ in self.segments]
+        outputs = [Signal(PMALayout()) for _ in self.segments]
 
         # zero output if addr not in region, propagate value if addr in region
         for i, segment in enumerate(self.segments):
@@ -64,6 +69,6 @@ def elaborate(self, platform) -> HasElaborate:
                 m.d.comb += outputs[i].eq(segment.mmio)
 
         # OR all outputs
-        m.d.comb += self.result.eq(reduce(or_, outputs, 0))
+        m.d.comb += self.result.eq(reduce(or_, [Value.cast(o) for o in outputs], 0))
 
         return m

coreblocks/params/layouts.py

@@ -18,7 +18,6 @@
     "UnsignedMulUnitLayouts",
     "RATLayouts",
     "LSULayouts",
-    "PMALayouts",
     "CSRLayouts",
     "ICacheLayouts",
     "JumpBranchLayouts",
@@ -551,11 +550,6 @@ def __init__(self, gen_params: GenParams):
         self.accept = make_layout(fields.data, fields.exception, fields.cause)
 
 
-class PMALayouts:
-    def __init__(self, gen_params: GenParams):
-        self.pma_attrs_layout = [("mmio", 1)]
-
-
 class CSRLayouts:
     """Layouts used in the control and status registers."""