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tilk committed Nov 19, 2024
1 parent 5ca7161 commit c3c1d59
Showing 1 changed file with 15 additions and 8 deletions.
23 changes: 15 additions & 8 deletions transactron/testing/infrastructure.py
Original file line number Diff line number Diff line change
Expand Up @@ -163,7 +163,19 @@ def __init__(
else:
self.ctx = nullcontext()

self.deadline = clk_period * max_cycles
self.timeouted = False

async def timeout_testbench(sim: SimulatorContext):
await sim.delay(clk_period * max_cycles)
self.timeouted = True

self.add_testbench(timeout_testbench, background=True)

def run(self) -> bool:
with self.ctx:
super().run()

return not self.timeouted


class TestCaseWithSimulator:
Expand Down Expand Up @@ -296,18 +308,13 @@ def run_simulation(self, module: HasElaborate, max_cycles: float = 10e4, add_tra

yield sim

async def timeout_testbench(sim: SimulatorContext):
await sim.delay(max_cycles * clk_period)
raise Exception(f"Simulation time limit exceeded ({max_cycles} clock cycles)")

sim.add_testbench(timeout_testbench, background=True)

for f in self._transactron_sim_processes_to_add:
ret = f()
if ret is not None:
sim.add_process(ret)

sim.run()
res = sim.run()
assert res, "Simulation time limit exceeded"

async def tick(self, sim: SimulatorContext, cycle_cnt: int = 1):
"""
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