Use clock neg edge instead of epsilon

kuznia-rdzeni · Feb 6, 2024 · bfe201e · bfe201e
1 parent 4d1ad11
commit bfe201e
Show file tree

Hide file tree

Showing 4 changed files with 10 additions and 8 deletions.
diff --git a/test/utils/test_assertion.py b/test/utils/test_assertion.py
@@ -26,7 +26,6 @@ def test_assertion(self):
         def proc():
             yield
             yield m.input.eq(1)
-            yield
 
         with self.assertRaises(AssertionError):
             with self.run_simulation(m) as sim:

diff --git a/transactron/testing/assertion.py b/transactron/testing/assertion.py
@@ -1,20 +1,20 @@
 from collections.abc import Callable
 from typing import Any
-from amaranth.sim import Passive, Delay
+from amaranth.sim import Passive, Tick
 from transactron.utils import assert_bit, assert_bits
 from transactron.utils.dependencies import DependencyContext
 
 
 __all__ = ["make_assert_handler"]
 
 
-def make_assert_handler(my_assert: Callable[[int, str], Any], clk_period: float):
+def make_assert_handler(my_assert: Callable[[int, str], Any]):
     dependency_manager = DependencyContext.get()
 
     def assert_handler():
         yield Passive()
         while True:
-            yield Delay((1 - 1e-4) * clk_period)  # Shorter than clock cycle
+            yield Tick("sync_neg")
             if not (yield assert_bit(dependency_manager)):
                 for v, (n, i) in assert_bits(dependency_manager):
                     my_assert((yield v), f"Assertion at {n}:{i}")

diff --git a/transactron/testing/infrastructure.py b/transactron/testing/infrastructure.py
@@ -110,6 +110,8 @@ def elaborate(self, platform) -> HasElaborate:
 
         m.submodules.tested_module = self.tested_module
 
+        m.domains.sync_neg = ClockDomain(clk_edge="neg", local=True)
+
         return m
 
 
@@ -161,6 +163,7 @@ def __init__(
         super().__init__(test_module)
 
         self.add_clock(clk_period)
+        self.add_clock(clk_period, domain="sync_neg")
 
         if isinstance(tested_module, HasDebugSignals):
             extra_signals = tested_module.debug_signals
@@ -257,10 +260,10 @@ def run_simulation(self, module: HasElaborate, max_cycles: float = 10e4, add_tra
         if "__TRANSACTRON_PROFILE" in os.environ and isinstance(sim.tested_module, TransactionModule):
             profile = Profile()
             sim.add_sync_process(
-                profiler_process(sim.tested_module.manager.get_dependency(TransactionManagerKey()), profile, clk_period)
+                profiler_process(sim.tested_module.manager.get_dependency(TransactionManagerKey()), profile)
             )
 
-        sim.add_sync_process(make_assert_handler(self.assertTrue, clk_period))
+        sim.add_sync_process(make_assert_handler(self.assertTrue))
 
         res = sim.run()
 

diff --git a/transactron/testing/profiler.py b/transactron/testing/profiler.py
@@ -8,7 +8,7 @@
 __all__ = ["profiler_process"]
 
 
-def profiler_process(transaction_manager: TransactionManager, profile: Profile, clk_period: float):
+def profiler_process(transaction_manager: TransactionManager, profile: Profile):
     def process() -> TestGen:
         method_map = MethodMap(transaction_manager.transactions)
         cgr, _, _ = TransactionManager._conflict_graph(method_map)
@@ -39,7 +39,7 @@ def local_src_loc(src_loc: SrcLoc):
 
         yield Passive()
         while True:
-            yield Delay((1 - 1e-4) * clk_period)  # shorter than one clock cycle
+            yield Tick("sync_neg")
 
             cprof = CycleProfile()
             profile.cycles.append(cprof)