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@@ -35,6 +35,7 @@ | |
.endm | ||
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.macro INIT_REGS_ALLOCATION | ||
.org 0x100 | ||
.section .init_regs, "a", @nobits | ||
.skip 0x80 | ||
.previous | ||
.endm |
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@@ -101,5 +101,4 @@ fail: | |
j int_handler | ||
li x31, 0xae # should never happen | ||
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.bss | ||
INIT_REGS_ALLOCATION | ||
INIT_REGS_ALLOCATION |
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@@ -1,11 +1,17 @@ | ||
OUTPUT_ARCH( "riscv" ) | ||
OTPUT_ARCH( "riscv" ) | ||
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start = 0; | ||
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SECTIONS | ||
{ | ||
.text : { *(.text) } | ||
. = 0x100000000; /* start from 2**32 - trick to emulate Harvard architecture (memory addresses will start from 0) */ | ||
.data : { *(.data) *(.bss) } | ||
_end = .; | ||
.data : { | ||
*(.data) | ||
*(.bss) | ||
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. = _end_init_regs > . ? 0x1000 : .; /* skip .init_regs origin allocation if not used */ | ||
*(.init_regs) | ||
_end_init_regs = .; | ||
} | ||
} |
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@@ -29,5 +29,4 @@ skip: | |
.org 0x100 | ||
j handler | ||
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.data | ||
INIT_REGS_ALLOCATION | ||
INIT_REGS_ALLOCATION |