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Merge branch 'master' into lekcyjna/update-synthesis-doc
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lekcyjna123 authored Nov 13, 2023
2 parents ebae77d + 78f66cc commit 996b088
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34 changes: 27 additions & 7 deletions .github/workflows/benchmark.yml
Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,7 @@ jobs:
name: Synthesis benchmarks
runs-on: ubuntu-latest
timeout-minutes: 40
container: ghcr.io/kuznia-rdzeni/amaranth-synth:ecp5
container: ghcr.io/kuznia-rdzeni/amaranth-synth:ecp5-3.11
steps:
- uses: actions/checkout@v3

Expand All @@ -23,19 +23,29 @@ jobs:
# https://github.com/actions/runner/issues/2033
chown -R $(id -u):$(id -g) $PWD
- name: Set up Python
uses: actions/setup-python@v4
with:
python-version: '3.11'

- name: Install dependencies
run: |
python3 -m venv venv
. venv/bin/activate
python3 -m pip install --upgrade pip
pip3 install -r requirements-dev.txt
python3 -m pip install -r requirements-dev.txt
- name: Synthesize
run: PYTHONHASHSEED=0 ./scripts/synthesize.py --verbose --config ${{ matrix.config }}
run: |
. venv/bin/activate
PYTHONHASHSEED=0 ./scripts/synthesize.py --verbose --config ${{ matrix.config }}
- name: Print synthesis information
run: cat ./build/top.tim

- name: Collect Benchmark information
run: |
. venv/bin/activate
./scripts/parse_benchmark_info.py
cat ./benchmark.json
Expand All @@ -53,7 +63,7 @@ jobs:
build-perf-benchmarks:
name: Build performance benchmarks
runs-on: ubuntu-latest
container: ghcr.io/kuznia-rdzeni/riscv-toolchain:2023.05.14
container: ghcr.io/kuznia-rdzeni/riscv-toolchain:2023.10.08_v
steps:
- name: Checkout
uses: actions/checkout@v3
Expand All @@ -73,7 +83,7 @@ jobs:
name: Run performance benchmarks
runs-on: ubuntu-latest
timeout-minutes: 60
container: ghcr.io/kuznia-rdzeni/verilator:v5.008
container: ghcr.io/kuznia-rdzeni/verilator:v5.008-3.11
needs: build-perf-benchmarks
steps:
- name: Checkout
Expand All @@ -84,13 +94,22 @@ jobs:
# https://github.com/actions/runner/issues/2033
chown -R $(id -u):$(id -g) $PWD
- name: Set up Python
uses: actions/setup-python@v4
with:
python-version: '3.11'

- name: Install dependencies
run: |
python3 -m venv venv
. venv/bin/activate
python3 -m pip install --upgrade pip
pip3 install -r requirements-dev.txt
python3 -m pip install -r requirements-dev.txt
- name: Generate Verilog
run: PYTHONHASHSEED=0 ./scripts/gen_verilog.py --verbose --config full
run: |
. venv/bin/activate
PYTHONHASHSEED=0 ./scripts/gen_verilog.py --verbose --config full
- uses: actions/download-artifact@v3
with:
Expand All @@ -99,6 +118,7 @@ jobs:

- name: Run benchmarks
run: |
. venv/bin/activate
scripts/run_benchmarks.py
- name: Store benchmark result (IPC)
Expand Down
18 changes: 10 additions & 8 deletions .github/workflows/deploy_gh_pages.yml
Original file line number Diff line number Diff line change
Expand Up @@ -26,21 +26,23 @@ jobs:
- name: Set up Python
uses: actions/setup-python@v4
with:
python-version: "3.10"
cache: "pip"
cache-dependency-path: |
requirements.txt
requirements-dev.txt
python-version: "3.11"

- name: Install dependencies
run: |
python3 -m venv venv
. venv/bin/activate
python -m pip install --upgrade pip
pip3 install -r requirements-dev.txt
python -m pip install -r requirements-dev.txt
- name: Build documentation
run: ./ci/build_docs.sh
run: |
. venv/bin/activate
./ci/build_docs.sh
- name: Push documentation
# Deploy documentation only when on master
if: github.ref == 'refs/heads/master'
run: ./ci/push_gh_pages.sh
run: |
. venv/bin/activate
./ci/push_gh_pages.sh
22 changes: 16 additions & 6 deletions .github/workflows/main.yml
Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,7 @@ jobs:
build-regression-tests:
name: Build regression tests
runs-on: ubuntu-latest
container: ghcr.io/kuznia-rdzeni/riscv-toolchain:2023.05.14
container: ghcr.io/kuznia-rdzeni/riscv-toolchain:2023.10.08_v
steps:
- name: Checkout
uses: actions/checkout@v3
Expand All @@ -35,19 +35,28 @@ jobs:
name: Run regression tests
runs-on: ubuntu-latest
timeout-minutes: 10
container: ghcr.io/kuznia-rdzeni/verilator:v5.008
container: ghcr.io/kuznia-rdzeni/verilator:v5.008-3.11
needs: build-regression-tests
steps:
- name: Checkout
uses: actions/checkout@v3

- name: Set up Python
uses: actions/setup-python@v4
with:
python-version: '3.11'

- name: Install dependencies
run: |
python3 -m venv venv
. venv/bin/activate
python3 -m pip install --upgrade pip
pip3 install -r requirements-dev.txt
python3 -m pip install -r requirements-dev.txt
- name: Generate Verilog
run: PYTHONHASHSEED=0 ./scripts/gen_verilog.py --verbose --config full
run: |
. venv/bin/activate
PYTHONHASHSEED=0 ./scripts/gen_verilog.py --verbose --config full
- uses: actions/download-artifact@v3
with:
Expand All @@ -56,6 +65,7 @@ jobs:

- name: Run tests
run: |
. venv/bin/activate
scripts/run_tests.py -a regression
- name: Test Report
Expand All @@ -76,7 +86,7 @@ jobs:
- name: Set up Python
uses: actions/setup-python@v4
with:
python-version: '3.10'
python-version: '3.11'
cache: 'pip'
cache-dependency-path: |
requirements.txt
Expand Down Expand Up @@ -105,7 +115,7 @@ jobs:
- name: Set up Python
uses: actions/setup-python@v4
with:
python-version: '3.10'
python-version: '3.11'
cache: 'pip'
cache-dependency-path: |
requirements.txt
Expand Down
8 changes: 5 additions & 3 deletions constants/ecp5_platforms.py
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@
from constants.ecp5_pinout import ecp5_bg756_pins, ecp5_bg756_pclk

from coreblocks.peripherals.wishbone import WishboneParameters
from coreblocks.transactions.lib import AdapterBase
from transactron.lib import AdapterBase

__all__ = ["make_ecp5_platform"]

Expand Down Expand Up @@ -55,11 +55,12 @@ def __init__(self, pins: Iterable[str]):
def p(self, count: int = 1):
return " ".join([self.pin_bag.pop() for _ in range(count)])

def named_pin(self, names: list[str]):
def named_pin(self, names: Iterable[str]):
for name in names:
if name in self.pin_bag:
self.pin_bag.remove(name)
return name
raise RuntimeError("Named pins %s not free" % ", ".join(names))


ResourceBuilder: TypeAlias = Callable[[PinManager], list[Resource]]
Expand Down Expand Up @@ -123,9 +124,10 @@ class ECP5BG756Platform(LatticeECP5Platform):
default_clk = "clk"
default_rst = "rst"

clk_pin = pins.named_pin(ecp5_bg756_pclk)
resources = [
Resource("rst", 0, PinsN(pins.p(), dir="i"), Attrs(IO_TYPE="LVCMOS33")),
Resource("clk", 0, Pins(pins.named_pin(ecp5_bg756_pclk), dir="i"), Clock(12e6), Attrs(IO_TYPE="LVCMOS33")),
Resource("clk", 0, Pins(clk_pin, dir="i"), Clock(12e6), Attrs(IO_TYPE="LVCMOS33")),
] + resource_builder(pins)

connectors = []
Expand Down
6 changes: 3 additions & 3 deletions coreblocks/core.py
Original file line number Diff line number Diff line change
Expand Up @@ -2,8 +2,8 @@

from coreblocks.params.dependencies import DependencyManager
from coreblocks.stages.func_blocks_unifier import FuncBlocksUnifier
from coreblocks.transactions.core import Transaction, TModule
from coreblocks.transactions.lib import FIFO, ConnectTrans
from transactron.core import Transaction, TModule
from transactron.lib import FIFO, ConnectTrans
from coreblocks.params.layouts import *
from coreblocks.params.keys import BranchResolvedKey, GenericCSRRegistersKey, InstructionPrecommitKey, WishboneDataKey
from coreblocks.params.genparams import GenParams
Expand All @@ -20,7 +20,7 @@
from coreblocks.frontend.icache import ICache, SimpleWBCacheRefiller, ICacheBypass
from coreblocks.peripherals.wishbone import WishboneMaster, WishboneBus
from coreblocks.frontend.fetch import Fetch, UnalignedFetch
from coreblocks.utils.fifo import BasicFifo
from transactron.utils.fifo import BasicFifo

__all__ = ["Core"]

Expand Down
2 changes: 1 addition & 1 deletion coreblocks/frontend/decode.py
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@

from coreblocks.params.isa import Funct3
from coreblocks.params.optypes import OpType
from ..transactions import Method, Transaction, TModule
from transactron import Method, Transaction, TModule
from ..params import GenParams
from .decoder import InstrDecoder
from coreblocks.params import *
Expand Down
4 changes: 2 additions & 2 deletions coreblocks/frontend/fetch.py
Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
from amaranth import *
from coreblocks.utils.fifo import BasicFifo, Semaphore
from transactron.utils.fifo import BasicFifo, Semaphore
from coreblocks.frontend.icache import ICacheInterface
from coreblocks.frontend.rvc import InstrDecompress, is_instr_compressed
from ..transactions import def_method, Method, Transaction, TModule
from transactron import def_method, Method, Transaction, TModule
from ..params import *


Expand Down
31 changes: 22 additions & 9 deletions coreblocks/frontend/icache.py
Original file line number Diff line number Diff line change
Expand Up @@ -5,12 +5,12 @@
from amaranth import *
from amaranth.utils import log2_int

from coreblocks.transactions.core import def_method, Priority, TModule
from coreblocks.transactions import Method, Transaction
from transactron.core import def_method, Priority, TModule
from transactron import Method, Transaction
from coreblocks.params import ICacheLayouts, ICacheParameters
from coreblocks.utils import assign, OneHotSwitchDynamic
from coreblocks.utils._typing import HasElaborate
from coreblocks.transactions.lib import *
from transactron.utils import assign, OneHotSwitchDynamic
from transactron.utils._typing import HasElaborate
from transactron.lib import *
from coreblocks.peripherals.wishbone import WishboneMaster


Expand Down Expand Up @@ -382,30 +382,43 @@ def elaborate(self, platform):
refill_active = Signal()
word_counter = Signal(range(self.params.words_in_block))

with Transaction().body(m, request=refill_active):
m.submodules.address_fwd = address_fwd = Forwarder(
[("word_counter", word_counter.shape()), ("refill_address", refill_address.shape())]
)

with Transaction().body(m):
address = address_fwd.read(m)
self.wb_master.request(
m,
addr=Cat(word_counter, refill_address),
addr=Cat(address["word_counter"], address["refill_address"]),
data=0,
we=0,
sel=Repl(1, self.wb_master.wb_params.data_width // self.wb_master.wb_params.granularity),
)

@def_method(m, self.start_refill, ready=~refill_active)
def _(addr) -> None:
m.d.sync += refill_address.eq(addr[self.params.offset_bits :])
address = addr[self.params.offset_bits :]
m.d.sync += refill_address.eq(address)
m.d.sync += refill_active.eq(1)
m.d.sync += word_counter.eq(0)

address_fwd.write(m, word_counter=0, refill_address=address)

@def_method(m, self.accept_refill, ready=refill_active)
def _():
fetched = self.wb_master.result(m)

last = (word_counter == (self.params.words_in_block - 1)) | fetched.err

m.d.sync += word_counter.eq(word_counter + 1)
next_word_counter = Signal.like(word_counter)
m.d.top_comb += next_word_counter.eq(word_counter + 1)

m.d.sync += word_counter.eq(next_word_counter)
with m.If(last):
m.d.sync += refill_active.eq(0)
with m.Else():
address_fwd.write(m, word_counter=next_word_counter, refill_address=refill_address)

return {
"addr": Cat(Repl(0, log2_int(self.params.word_width_bytes)), word_counter, refill_address),
Expand Down
4 changes: 2 additions & 2 deletions coreblocks/frontend/rvc.py
Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
from amaranth import *

from coreblocks.transactions import TModule
from transactron import TModule
from coreblocks.params import *
from coreblocks.utils import ValueLike
from transactron.utils import ValueLike


# An instruction or an instruction with the valid signal
Expand Down
8 changes: 4 additions & 4 deletions coreblocks/fu/alu.py
Original file line number Diff line number Diff line change
@@ -1,18 +1,18 @@
from typing import Sequence
from amaranth import *

from coreblocks.transactions import *
from coreblocks.transactions.lib import FIFO
from transactron import *
from transactron.lib import FIFO

from coreblocks.params import OpType, Funct3, Funct7, GenParams, FuncUnitLayouts, FunctionalComponentParams
from coreblocks.utils import HasElaborate, OneHotSwitch
from transactron.utils import HasElaborate, OneHotSwitch

from coreblocks.fu.fu_decoder import DecoderManager
from enum import IntFlag, auto

from coreblocks.utils.protocols import FuncUnit

from coreblocks.utils.utils import popcount, count_leading_zeros
from transactron.utils.utils import popcount, count_leading_zeros

__all__ = ["AluFuncUnit", "ALUComponent"]

Expand Down
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