Fix test

kuznia-rdzeni · Nov 26, 2024 · 8a4f0bf · 8a4f0bf
1 parent 3117ef2
commit 8a4f0bf
Showing 1 changed file with 2 additions and 1 deletion.
diff --git a/test/test_core.py b/test/test_core.py
@@ -70,7 +70,8 @@ def get_phys_reg_rrat(self, sim: TestbenchContext, reg_id):
         return sim.get(self.m.core.RRAT.entries[reg_id])
 
     def get_arch_reg_val(self, sim: TestbenchContext, reg_id):
-        return sim.get(self.m.core.RF.entries[(self.get_phys_reg_rrat(sim, reg_id))].reg_val)
+        # TODO: better stubs for memory, remove ignore
+        return sim.get(self.m.core.RF.entries.data[(self.get_phys_reg_rrat(sim, reg_id))])  # type: ignore
 
 
 class TestCoreAsmSourceBase(TestCoreBase):