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Amaranth 0.5.3 (#754)
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@tilk
tilk authored Nov 25, 2024
1 parent 75c2706 commit 7e82d32
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Showing 9 changed files with 40 additions and 107 deletions.
2 changes: 1 addition & 1 deletion amaranth-stubs
Submodule amaranth-stubs updated 14 files
+0 −3 amaranth-stubs/_utils.pyi
+4 −1 amaranth-stubs/build/plat.pyi
+0 −9 amaranth-stubs/build/res.pyi
+2 −2 amaranth-stubs/hdl/__init__.pyi
+24 −2 amaranth-stubs/hdl/_ir.pyi
+9 −1 amaranth-stubs/lib/data.pyi
+8 −0 amaranth-stubs/lib/fifo.pyi
+95 −17 amaranth-stubs/lib/io.pyi
+97 −0 amaranth-stubs/lib/meta.pyi
+102 −0 amaranth-stubs/lib/stream.pyi
+35 −3 amaranth-stubs/lib/wiring.pyi
+1 −1 amaranth-stubs/sim/core.pyi
+1 −1 amaranth-stubs/sim/pysim.pyi
+2 −2 pyproject.toml
4 changes: 2 additions & 2 deletions coreblocks/core.py
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Original file line number Diff line number Diff line change
Expand Up @@ -96,8 +96,8 @@ def __init__(self, *, gen_params: GenParams):
def elaborate(self, platform):
m = TModule()

connect(m, flipped(self.wb_instr), self.wb_master_instr.wb_master)
connect(m, flipped(self.wb_data), self.wb_master_data.wb_master)
connect(m.top_module, flipped(self.wb_instr), self.wb_master_instr.wb_master)
connect(m.top_module, flipped(self.wb_data), self.wb_master_data.wb_master)

m.submodules.wb_master_instr = self.wb_master_instr
m.submodules.wb_master_data = self.wb_master_data
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2 changes: 1 addition & 1 deletion requirements.txt
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
./amaranth-stubs/ # can't use -e -- pyright doesn't see the stubs then :(
amaranth-yosys==0.40.0.0.post100
git+https://github.com/amaranth-lang/amaranth@994fa815995b1ac5b3c708915dcece2a45796569
amaranth==0.5.3
dataclasses-json==0.6.3
25 changes: 12 additions & 13 deletions test/func_blocks/fu/fpu/test_fpu_error.py
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Original file line number Diff line number Diff line change
Expand Up @@ -53,7 +53,7 @@ async def other_cases_test(sim: TestbenchContext):
"sig": help_values.not_max_norm_even_sig,
"exp": help_values.not_max_norm_exp,
"inexact": 0,
"rounding_mode": RoundingModes.ROUND_NEAREST_AWAY.value,
"rounding_mode": RoundingModes.ROUND_NEAREST_AWAY,
"invalid_operation": 0,
"division_by_zero": 0,
"input_inf": 0,
Expand All @@ -64,7 +64,7 @@ async def other_cases_test(sim: TestbenchContext):
"sig": help_values.not_max_norm_even_sig,
"exp": help_values.not_max_norm_exp,
"inexact": 1,
"rounding_mode": RoundingModes.ROUND_NEAREST_AWAY.value,
"rounding_mode": RoundingModes.ROUND_NEAREST_AWAY,
"invalid_operation": 0,
"division_by_zero": 0,
"input_inf": 0,
Expand All @@ -75,7 +75,7 @@ async def other_cases_test(sim: TestbenchContext):
"sig": help_values.sub_norm_sig,
"exp": 0,
"inexact": 1,
"rounding_mode": RoundingModes.ROUND_NEAREST_AWAY.value,
"rounding_mode": RoundingModes.ROUND_NEAREST_AWAY,
"invalid_operation": 0,
"division_by_zero": 0,
"input_inf": 0,
Expand All @@ -86,7 +86,7 @@ async def other_cases_test(sim: TestbenchContext):
"sig": help_values.qnan,
"exp": help_values.max_exp,
"inexact": 1,
"rounding_mode": RoundingModes.ROUND_NEAREST_AWAY.value,
"rounding_mode": RoundingModes.ROUND_NEAREST_AWAY,
"invalid_operation": 1,
"division_by_zero": 0,
"input_inf": 0,
Expand All @@ -97,7 +97,7 @@ async def other_cases_test(sim: TestbenchContext):
"sig": 0,
"exp": help_values.max_exp,
"inexact": 1,
"rounding_mode": RoundingModes.ROUND_NEAREST_AWAY.value,
"rounding_mode": RoundingModes.ROUND_NEAREST_AWAY,
"invalid_operation": 0,
"division_by_zero": 1,
"input_inf": 0,
Expand All @@ -108,7 +108,7 @@ async def other_cases_test(sim: TestbenchContext):
"sig": 0,
"exp": help_values.max_exp,
"inexact": 0,
"rounding_mode": RoundingModes.ROUND_NEAREST_AWAY.value,
"rounding_mode": RoundingModes.ROUND_NEAREST_AWAY,
"invalid_operation": 0,
"division_by_zero": 0,
"input_inf": 0,
Expand All @@ -119,7 +119,7 @@ async def other_cases_test(sim: TestbenchContext):
"sig": help_values.sub_norm_sig,
"exp": 0,
"inexact": 0,
"rounding_mode": RoundingModes.ROUND_NEAREST_AWAY.value,
"rounding_mode": RoundingModes.ROUND_NEAREST_AWAY,
"invalid_operation": 0,
"division_by_zero": 0,
"input_inf": 0,
Expand All @@ -130,7 +130,7 @@ async def other_cases_test(sim: TestbenchContext):
"sig": help_values.qnan,
"exp": help_values.max_exp,
"inexact": 1,
"rounding_mode": RoundingModes.ROUND_NEAREST_AWAY.value,
"rounding_mode": RoundingModes.ROUND_NEAREST_AWAY,
"invalid_operation": 0,
"division_by_zero": 0,
"input_inf": 0,
Expand All @@ -141,7 +141,7 @@ async def other_cases_test(sim: TestbenchContext):
"sig": 0,
"exp": help_values.max_exp,
"inexact": 1,
"rounding_mode": RoundingModes.ROUND_NEAREST_AWAY.value,
"rounding_mode": RoundingModes.ROUND_NEAREST_AWAY,
"invalid_operation": 0,
"division_by_zero": 0,
"input_inf": 1,
Expand All @@ -152,7 +152,7 @@ async def other_cases_test(sim: TestbenchContext):
"sig": help_values.min_norm_sig,
"exp": 0,
"inexact": 1,
"rounding_mode": RoundingModes.ROUND_NEAREST_AWAY.value,
"rounding_mode": RoundingModes.ROUND_NEAREST_AWAY,
"invalid_operation": 0,
"division_by_zero": 0,
"input_inf": 0,
Expand Down Expand Up @@ -262,14 +262,13 @@ def test_rounding(
fpue = TestFPUError.FPUErrorModule(params)

async def one_rounding_mode_test(sim: TestbenchContext):
rm_int = rm.value # TODO: workaround for amaranth bug
test_cases = [
# overflow detection
{
"sign": 0,
"sig": 0,
"exp": help_values.max_exp,
"rounding_mode": rm_int,
"rounding_mode": rm,
"inexact": 0,
"invalid_operation": 0,
"division_by_zero": 0,
Expand All @@ -279,7 +278,7 @@ async def one_rounding_mode_test(sim: TestbenchContext):
"sign": 1,
"sig": 0,
"exp": help_values.max_exp,
"rounding_mode": rm_int,
"rounding_mode": rm,
"inexact": 0,
"invalid_operation": 0,
"division_by_zero": 0,
Expand Down
23 changes: 11 additions & 12 deletions test/func_blocks/fu/fpu/test_fpu_rounding.py
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Original file line number Diff line number Diff line change
Expand Up @@ -96,7 +96,6 @@ def test_rounding(
fpurt = TestFPURounding.FPURoundingModule(params)

async def one_rounding_mode_test(sim: TestbenchContext):
rm_int = rm.value # TODO: workaround for Amaranth bug
test_cases = [
# carry after increment
{
Expand All @@ -105,7 +104,7 @@ async def one_rounding_mode_test(sim: TestbenchContext):
"exp": help_values.not_max_norm_exp,
"round_bit": 1,
"sticky_bit": 1,
"rounding_mode": rm_int,
"rounding_mode": rm,
},
# no overflow 00
{
Expand All @@ -114,15 +113,15 @@ async def one_rounding_mode_test(sim: TestbenchContext):
"exp": help_values.not_max_norm_exp,
"round_bit": 0,
"sticky_bit": 0,
"rounding_mode": rm_int,
"rounding_mode": rm,
},
{
"sign": 1,
"sig": help_values.not_max_norm_sig,
"exp": help_values.not_max_norm_exp,
"round_bit": 0,
"sticky_bit": 0,
"rounding_mode": rm_int,
"rounding_mode": rm,
},
# no overflow 10
{
Expand All @@ -131,15 +130,15 @@ async def one_rounding_mode_test(sim: TestbenchContext):
"exp": help_values.not_max_norm_exp,
"round_bit": 1,
"sticky_bit": 0,
"rounding_mode": rm_int,
"rounding_mode": rm,
},
{
"sign": 1,
"sig": help_values.not_max_norm_sig,
"exp": help_values.not_max_norm_exp,
"round_bit": 1,
"sticky_bit": 0,
"rounding_mode": rm_int,
"rounding_mode": rm,
},
# no overflow 01
{
Expand All @@ -148,15 +147,15 @@ async def one_rounding_mode_test(sim: TestbenchContext):
"exp": help_values.not_max_norm_exp,
"round_bit": 0,
"sticky_bit": 1,
"rounding_mode": rm_int,
"rounding_mode": rm,
},
{
"sign": 1,
"sig": help_values.not_max_norm_sig,
"exp": help_values.not_max_norm_exp,
"round_bit": 0,
"sticky_bit": 1,
"rounding_mode": rm_int,
"rounding_mode": rm,
},
# no overflow 11
{
Expand All @@ -165,15 +164,15 @@ async def one_rounding_mode_test(sim: TestbenchContext):
"exp": help_values.not_max_norm_exp,
"round_bit": 1,
"sticky_bit": 1,
"rounding_mode": rm_int,
"rounding_mode": rm,
},
{
"sign": 1,
"sig": help_values.not_max_norm_sig,
"exp": help_values.not_max_norm_exp,
"round_bit": 1,
"sticky_bit": 1,
"rounding_mode": rm_int,
"rounding_mode": rm,
},
# Round to nearest tie to even
{
Expand All @@ -182,15 +181,15 @@ async def one_rounding_mode_test(sim: TestbenchContext):
"exp": help_values.not_max_norm_exp,
"round_bit": 1,
"sticky_bit": 0,
"rounding_mode": rm_int,
"rounding_mode": rm,
},
{
"sign": 0,
"sig": help_values.not_max_norm_even_sig,
"exp": help_values.not_max_norm_exp,
"round_bit": 1,
"sticky_bit": 0,
"rounding_mode": rm_int,
"rounding_mode": rm,
},
]
expected_results = [
Expand Down
2 changes: 2 additions & 0 deletions test/transactron/testing/test_log.py
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Original file line number Diff line number Diff line change
Expand Up @@ -95,6 +95,7 @@ def test_error_log(self, caplog):
async def proc(sim: TestbenchContext):
await sim.tick()
sim.set(m.input, 1)
await sim.tick() # A log after the last tick is not handled

with pytest.raises(AssertionError):
with self.run_simulation(m) as sim:
Expand All @@ -112,6 +113,7 @@ def test_assertion(self, caplog):
async def proc(sim: TestbenchContext):
await sim.tick()
sim.set(m.input, 1)
await sim.tick() # A log after the last tick is not handled

with pytest.raises(AssertionError):
with self.run_simulation(m) as sim:
Expand Down
71 changes: 0 additions & 71 deletions transactron/testing/gtkw_extension.py
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This file was deleted.

16 changes: 10 additions & 6 deletions transactron/testing/infrastructure.py
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Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,6 @@
from .profiler import profiler_process, Profile
from .logging import make_logging_process, parse_logging_level, _LogFormatter
from .tick_count import make_tick_count_process
from .gtkw_extension import write_vcd_ext
from .method_mock import MethodMock
from transactron import Method
from transactron.lib import AdapterTrans
Expand Down Expand Up @@ -156,22 +155,27 @@ def __init__(
extra_signals = extra_signals()
clocks = [d.clk for d in cast(Any, self)._design.fragment.domains.values()]

self.ctx = write_vcd_ext(
cast(Any, self)._engine,
self.ctx = self.write_vcd(
f"{traces_dir}/{traces_file}.vcd",
f"{traces_dir}/{traces_file}.gtkw",
traces=[clocks, extra_signals],
)
else:
self.ctx = nullcontext()

self.deadline = clk_period * max_cycles
self.timeouted = False

async def timeout_testbench(sim: SimulatorContext):
await sim.delay(clk_period * max_cycles)
self.timeouted = True

self.add_testbench(timeout_testbench, background=True)

def run(self) -> bool:
with self.ctx:
self.run_until(self.deadline)
super().run()

return not self.advance()
return not self.timeouted


class TestCaseWithSimulator:
Expand Down
2 changes: 1 addition & 1 deletion transactron/testing/logging.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -97,7 +97,7 @@ async def log_process(sim: ProcessContext) -> None:
ticks = DependencyContext.get().get_dependency(TicksKey())

async for _, _, ticks_val, combined_trigger_val, *record_vals in (
sim.tick("sync_neg")
sim.tick()
.sample(ticks, combined_trigger)
.sample(*itertools.chain(*([record.trigger] + record.fields for record in records)))
):
Expand Down

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