Merge branch 'master' into tilk/lib-wiring-migration

.github/workflows/benchmark.yml

@@ -63,7 +63,7 @@ jobs:
   build-perf-benchmarks:
     name: Build performance benchmarks
     runs-on: ubuntu-latest
-    container: ghcr.io/kuznia-rdzeni/riscv-toolchain:2023.11.19_v
+    container: ghcr.io/kuznia-rdzeni/riscv-toolchain:2024.03.12
     steps:
       - name: Checkout
         uses: actions/checkout@v3

.github/workflows/main.yml

@@ -48,7 +48,7 @@ jobs:
   build-riscof-tests:
     name: Build regression tests (riscv-arch-test)
     runs-on: ubuntu-latest
-    container: ghcr.io/kuznia-rdzeni/riscv-toolchain:2023.11.19_v
+    container: ghcr.io/kuznia-rdzeni/riscv-toolchain:2024.03.12
     timeout-minutes: 10
     env:
       PYENV_ROOT: "/root/.pyenv"
@@ -180,7 +180,7 @@ jobs:
   build-regression-tests:
     name: Build regression tests (riscv-tests)
     runs-on: ubuntu-latest
-    container: ghcr.io/kuznia-rdzeni/riscv-toolchain:2023.11.19_v
+    container: ghcr.io/kuznia-rdzeni/riscv-toolchain:2024.03.12
     timeout-minutes: 10
     outputs:
         cache_hit: ${{ steps.cache-regression.outputs.cache-hit }}
@@ -263,6 +263,12 @@ jobs:
           . venv/bin/activate
           scripts/run_tests.py -a regression
 
+      - name: Check regression with pysim
+        run: |
+          . venv/bin/activate
+          ./scripts/run_tests.py -c 1 -a -b pysim regression
+
+
   unit-test:
     name: Run unit tests
     runs-on: ubuntu-latest
@@ -292,6 +298,9 @@ jobs:
       - name: Check traces and profiles
         run: ./scripts/run_tests.py -t -p -c 1 TestCore
 
+      - name: Check listing tests
+        run: ./scripts/run_tests.py -l
+
   lint:
     name: Check code formatting and typing
     runs-on: ubuntu-latest

docker/riscv-toolchain.Dockerfile

@@ -12,8 +12,8 @@ RUN apt-get update && \
 
 RUN git clone --shallow-since=2023.05.01 https://github.com/riscv/riscv-gnu-toolchain && \
     cd riscv-gnu-toolchain && \
-    git checkout 2023.05.14 && \
-    ./configure --with-multilib-generator="rv32i-ilp32--a*zifence*zicsr;rv32im-ilp32--a*zifence*zicsr;rv32ic-ilp32--a*zifence*zicsr;rv32imc-ilp32--a*zifence*zicsr;rv32imfc-ilp32f--a*zifence;rv32i_zmmul-ilp32--a*zifence*zicsr;rv32ic_zmmul-ilp32--a*zifence*zicsr" && \
+    git checkout 2023.12.10 && \
+    ./configure --with-multilib-generator="rv32i-ilp32--a*zifence*zicsr;rv32im-ilp32--a*zifence*zicsr;rv32ic-ilp32--a*zifence*zicsr;rv32imc-ilp32--a*zifence*zicsr;rv32imfc-ilp32f--a*zifence;rv32imc_zba_zbb_zbc_zbs-ilp32--a*zifence*zicsr" && \
     make -j$(nproc) && \
     cd / && rm -rf riscv-gnu-toolchain
 

test/external/embench/board_config/coreblocks-sim/board.cfg

@@ -1,5 +1,5 @@
 cc = 'riscv64-unknown-elf-gcc'
-cflags = (['-c', '-fdata-sections', '-march=rv32ic_zmmul_zicsr', '-mabi=ilp32'])
-ldflags = (['-Wl,-gc-sections', '-march=rv32ic_zmmul_zicsr', '-mabi=ilp32', '-nostartfiles', '-T../../../common/link.ld'])
+cflags = (['-c', '-fdata-sections', '-march=rv32imc_zba_zbb_zbc_zbs_zicsr', '-mabi=ilp32'])
+ldflags = (['-Wl,-gc-sections', '-march=rv32imc_zba_zbb_zbc_zbs_zicsr', '-mabi=ilp32', '-nostartfiles', '-T../../../common/link.ld'])
 user_libs = (['-lm'])
 cpu_mhz = 0.01

test/regression/cocotb.py

@@ -157,10 +157,9 @@ def get_cocotb_handle(self, path_components: list[str]) -> ModifiableObject:
                 # function instead of 'getattr' - this is required by cocotb.
                 obj = obj._id(component, extended=False)
             except AttributeError:
-                if component[0] == "\\" and component[-1] == " ":
-                    # workaround for cocotb/verilator weirdness
-                    # for some escaped names lookup fails, but works when unescaped
-                    obj = obj._id(component[1:-1], extended=False)
+                # Try with escaped name
+                if component[0] != "\\" and component[-1] != " ":
+                    obj = obj._id("\\" + component + " ", extended=False)
                 else:
                     raise
 

transactron/utils/gen.py

@@ -149,7 +149,7 @@ def escape_verilog_identifier(identifier: str) -> str:
     # The standard says how to escape a identifier, but not when. So this is
     # a non-exhaustive list of characters that Yosys escapes (it is used
     # by Amaranth when generating Verilog code).
-    characters_to_escape = [".", "$"]
+    characters_to_escape = [".", "$", "-"]
 
     for char in characters_to_escape:
         if char in identifier:
@@ -160,10 +160,7 @@ def escape_verilog_identifier(identifier: str) -> str:
 
 def get_signal_location(signal: Signal, name_map: "SignalDict") -> list[str]:
     raw_location = name_map[signal]
-
-    # Amaranth escapes identifiers when generating Verilog code, but returns non-escaped identifiers
-    # in the name map, so we need to escape it manually.
-    return [escape_verilog_identifier(component) for component in raw_location]
+    return raw_location
 
 
 def collect_metric_locations(name_map: "SignalDict") -> dict[str, MetricLocation]: