Skip to content

Commit

Permalink
Merge branch 'master' into superscalar_icache
Browse files Browse the repository at this point in the history
  • Loading branch information
Jacob Urbanczyk committed Mar 25, 2024
2 parents fb1124e + 6128533 commit 77e6961
Show file tree
Hide file tree
Showing 13 changed files with 116 additions and 104 deletions.
14 changes: 7 additions & 7 deletions .github/workflows/benchmark.yml
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,15 +16,15 @@ jobs:
timeout-minutes: 40
container: ghcr.io/kuznia-rdzeni/amaranth-synth:ecp5-2023.11.19_v
steps:
- uses: actions/checkout@v3
- uses: actions/checkout@v4

- name: Set ownership (Github Actions workaround)
run: |
# https://github.com/actions/runner/issues/2033
chown -R $(id -u):$(id -g) $PWD
- name: Set up Python
uses: actions/setup-python@v4
uses: actions/setup-python@v5
with:
python-version: '3.11'

Expand Down Expand Up @@ -66,14 +66,14 @@ jobs:
container: ghcr.io/kuznia-rdzeni/riscv-toolchain:2024.03.12
steps:
- name: Checkout
uses: actions/checkout@v3
uses: actions/checkout@v4
with:
submodules: recursive

- name: Build embench
run: cd test/external/embench && make

- uses: actions/upload-artifact@v3
- uses: actions/upload-artifact@v4
with:
name: "embench"
path: |
Expand All @@ -87,15 +87,15 @@ jobs:
needs: build-perf-benchmarks
steps:
- name: Checkout
uses: actions/checkout@v3
uses: actions/checkout@v4

- name: Set ownership (Github Actions workaround)
run: |
# https://github.com/actions/runner/issues/2033
chown -R $(id -u):$(id -g) $PWD
- name: Set up Python
uses: actions/setup-python@v4
uses: actions/setup-python@v5
with:
python-version: '3.11'

Expand All @@ -111,7 +111,7 @@ jobs:
. venv/bin/activate
PYTHONHASHSEED=0 TRANSACTRON_VERBOSE=1 ./scripts/gen_verilog.py --verbose --config full
- uses: actions/download-artifact@v3
- uses: actions/download-artifact@v4
with:
name: "embench"
path: test/external/embench/build
Expand Down
4 changes: 2 additions & 2 deletions .github/workflows/deploy_gh_pages.yml
View file
Original file line number Diff line number Diff line change
Expand Up @@ -21,10 +21,10 @@ jobs:
BUILD_DIR: "build"
steps:
- name: Checkout
uses: actions/checkout@v3
uses: actions/checkout@v4

- name: Set up Python
uses: actions/setup-python@v4
uses: actions/setup-python@v5
with:
python-version: "3.11"

Expand Down
46 changes: 23 additions & 23 deletions .github/workflows/main.yml
View file
Original file line number Diff line number Diff line change
Expand Up @@ -18,10 +18,10 @@ jobs:
timeout-minutes: 5
steps:
- name: Checkout
uses: actions/checkout@v3
uses: actions/checkout@v4

- name: Set up Python
uses: actions/setup-python@v4
uses: actions/setup-python@v5
with:
python-version: '3.11'

Expand All @@ -37,7 +37,7 @@ jobs:
. venv/bin/activate
PYTHONHASHSEED=0 TRANSACTRON_VERBOSE=1 ./scripts/gen_verilog.py --verbose --config full
- uses: actions/upload-artifact@v3
- uses: actions/upload-artifact@v4
with:
name: "verilog-full-core"
path: |
Expand All @@ -60,7 +60,7 @@ jobs:

steps:
- name: Checkout
uses: actions/checkout@v3
uses: actions/checkout@v4

- name: Get submodules HEAD hash
working-directory: .
Expand All @@ -72,7 +72,7 @@ jobs:
- name: Cache compiled and reference riscv-arch-test
id: cache-riscv-arch-test
uses: actions/cache@v3
uses: actions/cache@v4
env:
cache-name: cache-riscv-arch-test
with:
Expand All @@ -93,7 +93,7 @@ jobs:

- if: ${{ steps.cache-riscv-arch-test.outputs.cache-hit != 'true' }}
name: Checkout with submodules
uses: actions/checkout@v3
uses: actions/checkout@v4
with:
submodules: recursive

Expand Down Expand Up @@ -127,7 +127,7 @@ jobs:
- if: ${{ steps.cache-riscv-arch-test.outputs.cache-hit != 'true' }}
name: Upload compiled and reference tests artifact
uses: actions/upload-artifact@v3
uses: actions/upload-artifact@v4
with:
name: "riscof-tests"
path: |
Expand All @@ -143,10 +143,10 @@ jobs:
timeout-minutes: 30
steps:
- name: Checkout
uses: actions/checkout@v3
uses: actions/checkout@v4

- name: Set up Python
uses: actions/setup-python@v4
uses: actions/setup-python@v5
with:
python-version: '3.11'

Expand All @@ -157,7 +157,7 @@ jobs:
python3 -m pip install --upgrade pip
python3 -m pip install -r requirements-dev.txt
- uses: actions/download-artifact@v3
- uses: actions/download-artifact@v4
name: Download full verilog core
with:
name: "verilog-full-core"
Expand All @@ -168,7 +168,7 @@ jobs:
git config --global --add safe.directory /__w/coreblocks/coreblocks
git submodule > .gitmodules-hash
- uses: actions/cache@v3
- uses: actions/cache@v4
name: Download tests from cache
env:
cache-name: cache-riscv-arch-test
Expand Down Expand Up @@ -204,7 +204,7 @@ jobs:
timeout-minutes: 10
steps:
- name: Checkout
uses: actions/checkout@v3
uses: actions/checkout@v4

- name: Get submodules HEAD hash
run: |
Expand All @@ -213,7 +213,7 @@ jobs:
- name: Cache regression-tests
id: cache-regression
uses: actions/cache@v3
uses: actions/cache@v4
env:
cache-name: cache-regression-tests
with:
Expand All @@ -229,7 +229,7 @@ jobs:

- if: ${{ steps.cache-regression.outputs.cache-hit != 'true' }}
name: Checkout with submodules
uses: actions/checkout@v3
uses: actions/checkout@v4
with:
submodules: recursive

Expand All @@ -238,7 +238,7 @@ jobs:

- if: ${{ steps.cache-regression.outputs.cache-hit != 'true' }}
name: Upload riscv-tests
uses: actions/upload-artifact@v3
uses: actions/upload-artifact@v4
with:
path: test/external/riscv-tests

Expand All @@ -250,10 +250,10 @@ jobs:
needs: [ build-regression-tests, build-core ]
steps:
- name: Checkout
uses: actions/checkout@v3
uses: actions/checkout@v4

- name: Set up Python
uses: actions/setup-python@v4
uses: actions/setup-python@v5
with:
python-version: '3.11'

Expand All @@ -264,7 +264,7 @@ jobs:
python3 -m pip install --upgrade pip
python3 -m pip install -r requirements-dev.txt
- uses: actions/download-artifact@v3
- uses: actions/download-artifact@v4
name: Download full verilog core
with:
name: "verilog-full-core"
Expand All @@ -275,7 +275,7 @@ jobs:
git config --global --add safe.directory /__w/coreblocks/coreblocks
git submodule > .gitmodules-hash
- uses: actions/cache@v3
- uses: actions/cache@v4
name: Download tests from cache
env:
cache-name: cache-regression-tests
Expand Down Expand Up @@ -307,10 +307,10 @@ jobs:
timeout-minutes: 15
steps:
- name: Checkout
uses: actions/checkout@v3
uses: actions/checkout@v4

- name: Set up Python
uses: actions/setup-python@v4
uses: actions/setup-python@v5
with:
python-version: '3.11'
cache: 'pip'
Expand Down Expand Up @@ -339,10 +339,10 @@ jobs:
timeout-minutes: 5
steps:
- name: Checkout
uses: actions/checkout@v3
uses: actions/checkout@v4

- name: Set up Python
uses: actions/setup-python@v4
uses: actions/setup-python@v5
with:
python-version: '3.11'
cache: 'pip'
Expand Down
44 changes: 43 additions & 1 deletion coreblocks/params/instr.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@
from amaranth.hdl import ValueCastable
from amaranth import *

from transactron.utils import ValueLike
from transactron.utils import ValueLike, int_to_signed
from coreblocks.params.isa_params import *
from coreblocks.frontend.decoder.isa import *

Expand Down Expand Up @@ -53,6 +53,10 @@ def __init__(
def pack(self) -> Value:
return Cat(C(0b11, 2), self.opcode, self.rd, self.funct3, self.rs1, self.rs2, self.funct7)

@staticmethod
def encode(opcode: int, rd: int, funct3: int, rs1: int, rs2: int, funct7: int):
return int(f"{funct7:07b}{rs2:05b}{rs1:05b}{funct3:03b}{rd:05b}{opcode:05b}11", 2)


class ITypeInstr(RISCVInstr):
def __init__(self, opcode: ValueLike, rd: ValueLike, funct3: ValueLike, rs1: ValueLike, imm: ValueLike):
Expand All @@ -65,6 +69,11 @@ def __init__(self, opcode: ValueLike, rd: ValueLike, funct3: ValueLike, rs1: Val
def pack(self) -> Value:
return Cat(C(0b11, 2), self.opcode, self.rd, self.funct3, self.rs1, self.imm)

@staticmethod
def encode(opcode: int, rd: int, funct3: int, rs1: int, imm: int):
imm = int_to_signed(imm, 12)
return int(f"{imm:012b}{rs1:05b}{funct3:03b}{rd:05b}{opcode:05b}11", 2)


class STypeInstr(RISCVInstr):
def __init__(self, opcode: ValueLike, imm: ValueLike, funct3: ValueLike, rs1: ValueLike, rs2: ValueLike):
Expand All @@ -77,6 +86,12 @@ def __init__(self, opcode: ValueLike, imm: ValueLike, funct3: ValueLike, rs1: Va
def pack(self) -> Value:
return Cat(C(0b11, 2), self.opcode, self.imm[0:5], self.funct3, self.rs1, self.rs2, self.imm[5:12])

@staticmethod
def encode(opcode: int, imm: int, funct3: int, rs1: int, rs2: int):
imm = int_to_signed(imm, 12)
imm_str = f"{imm:012b}"
return int(f"{imm_str[5:12]:07b}{rs2:05b}{rs1:05b}{funct3:03b}{imm_str[0:5]:05b}{opcode:05b}11", 2)


class BTypeInstr(RISCVInstr):
def __init__(self, opcode: ValueLike, imm: ValueLike, funct3: ValueLike, rs1: ValueLike, rs2: ValueLike):
Expand All @@ -99,6 +114,16 @@ def pack(self) -> Value:
self.imm[12],
)

@staticmethod
def encode(opcode: int, imm: int, funct3: int, rs1: int, rs2: int):
imm = int_to_signed(imm, 13)
imm_str = f"{imm:013b}"
return int(
f"{imm_str[12]:01b}{imm_str[5:11]:06b}{rs2:05b}{rs1:05b}{funct3:03b}{imm_str[1:5]:04b}"
+ f"{imm_str[11]:01b}{opcode:05b}11",
2,
)


class UTypeInstr(RISCVInstr):
def __init__(self, opcode: ValueLike, rd: ValueLike, imm: ValueLike):
Expand All @@ -109,6 +134,11 @@ def __init__(self, opcode: ValueLike, rd: ValueLike, imm: ValueLike):
def pack(self) -> Value:
return Cat(C(0b11, 2), self.opcode, self.rd, self.imm[12:])

@staticmethod
def encode(opcode: int, rd: int, imm: int):
imm = int_to_signed(imm, 20)
return int(f"{imm:020b}{rd:05b}{opcode:05b}11", 2)


class JTypeInstr(RISCVInstr):
def __init__(self, opcode: ValueLike, rd: ValueLike, imm: ValueLike):
Expand All @@ -119,6 +149,14 @@ def __init__(self, opcode: ValueLike, rd: ValueLike, imm: ValueLike):
def pack(self) -> Value:
return Cat(C(0b11, 2), self.opcode, self.rd, self.imm[12:20], self.imm[11], self.imm[1:11], self.imm[20])

@staticmethod
def encode(opcode: int, rd: int, imm: int):
imm = int_to_signed(imm, 21)
imm_str = f"{imm:021b}"
return int(
f"{imm_str[20]:01b}{imm_str[1:11]:010b}{imm_str[11]:01b}{imm_str[12:20]:08b}{rd:05b}{opcode:05b}11", 2
)


class IllegalInstr(RISCVInstr):
def __init__(self):
Expand All @@ -127,6 +165,10 @@ def __init__(self):
def pack(self) -> Value:
return C(1).replicate(32) # Instructions with all bits set to 1 are reserved to be illegal.

@staticmethod
def encode(opcode: int, rd: int, imm: int):
return int("1" * 32, 2)


class EBreakInstr(ITypeInstr):
def __init__(self):
Expand Down
3 changes: 1 addition & 2 deletions requirements-dev.txt
View file
Original file line number Diff line number Diff line change
@@ -1,9 +1,8 @@
-r requirements.txt
black==23.3.0
black==24.3.0
docutils==0.15.2
flake8==6.0.0
pep8-naming==0.13.3
git+https://github.com/kristopher38/riscv-python-model@b5d0737#riscv-model
markupsafe==2.0.1
myst-parser==0.18.0
numpydoc==1.5.0
Expand Down
6 changes: 3 additions & 3 deletions test/lsu/test_dummylsu.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -173,9 +173,9 @@ def generate_instr(self, max_reg_val, max_imm_val):
self.exception_queue.append(
{
"rob_id": rob_id,
"cause": ExceptionCause.LOAD_ADDRESS_MISALIGNED
if misaligned
else ExceptionCause.LOAD_ACCESS_FAULT,
"cause": (
ExceptionCause.LOAD_ADDRESS_MISALIGNED if misaligned else ExceptionCause.LOAD_ACCESS_FAULT
),
"pc": 0,
}
)
Expand Down
1 change: 1 addition & 0 deletions test/regression/cocotb/benchmark.Makefile
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,6 +15,7 @@ SIM_BUILD = build/benchmark
# Yosys/Amaranth borkedness workaround
ifeq ($(SIM),verilator)
EXTRA_ARGS += -Wno-CASEINCOMPLETE -Wno-CASEOVERLAP -Wno-WIDTHEXPAND -Wno-WIDTHTRUNC
BUILD_ARGS += -j`nproc`
endif

ifeq ($(TRACES),1)
Expand Down
1 change: 1 addition & 0 deletions test/regression/cocotb/signature.Makefile
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,6 +15,7 @@ SIM_BUILD = build/signature
# Yosys/Amaranth borkedness workaround
ifeq ($(SIM),verilator)
EXTRA_ARGS += -Wno-CASEINCOMPLETE -Wno-CASEOVERLAP -Wno-WIDTHEXPAND -Wno-WIDTHTRUNC
BUILD_ARGS += -j`nproc`
endif

ifeq ($(TRACES),1)
Expand Down
Loading

0 comments on commit 77e6961

Please sign in to comment.