Move coreblocks utils to transactron (#503)

Co-authored-by: Lekcyjna <[email protected]>
Co-authored-by: Marek Materzok <[email protected]>

coreblocks/core.py

@@ -20,7 +20,7 @@
 from coreblocks.frontend.icache import ICache, SimpleWBCacheRefiller, ICacheBypass
 from coreblocks.peripherals.wishbone import WishboneMaster, WishboneBus
 from coreblocks.frontend.fetch import Fetch, UnalignedFetch
-from coreblocks.utils.fifo import BasicFifo
+from transactron.utils.fifo import BasicFifo
 
 __all__ = ["Core"]
 

coreblocks/frontend/fetch.py

@@ -1,5 +1,5 @@
 from amaranth import *
-from coreblocks.utils.fifo import BasicFifo, Semaphore
+from transactron.utils.fifo import BasicFifo, Semaphore
 from coreblocks.frontend.icache import ICacheInterface
 from coreblocks.frontend.rvc import InstrDecompress, is_instr_compressed
 from transactron import def_method, Method, Transaction, TModule

coreblocks/frontend/icache.py

@@ -8,8 +8,8 @@
 from transactron.core import def_method, Priority, TModule
 from transactron import Method, Transaction
 from coreblocks.params import ICacheLayouts, ICacheParameters
-from coreblocks.utils import assign, OneHotSwitchDynamic
-from coreblocks.utils._typing import HasElaborate
+from transactron.utils import assign, OneHotSwitchDynamic
+from transactron.utils._typing import HasElaborate
 from transactron.lib import *
 from coreblocks.peripherals.wishbone import WishboneMaster
 

coreblocks/frontend/rvc.py

@@ -2,7 +2,7 @@
 
 from transactron import TModule
 from coreblocks.params import *
-from coreblocks.utils import ValueLike
+from transactron.utils import ValueLike
 
 
 # An instruction or an instruction with the valid signal

coreblocks/fu/alu.py

@@ -5,14 +5,14 @@
 from transactron.lib import FIFO
 
 from coreblocks.params import OpType, Funct3, Funct7, GenParams, FuncUnitLayouts, FunctionalComponentParams
-from coreblocks.utils import HasElaborate, OneHotSwitch
+from transactron.utils import HasElaborate, OneHotSwitch
 
 from coreblocks.fu.fu_decoder import DecoderManager
 from enum import IntFlag, auto
 
 from coreblocks.utils.protocols import FuncUnit
 
-from coreblocks.utils.utils import popcount, count_leading_zeros
+from transactron.utils.utils import popcount, count_leading_zeros
 
 __all__ = ["AluFuncUnit", "ALUComponent"]
 

coreblocks/fu/div_unit.py

@@ -12,8 +12,8 @@
 
 from coreblocks.fu.fu_decoder import DecoderManager
 
-from coreblocks.utils import OneHotSwitch
-from coreblocks.utils.fifo import BasicFifo
+from transactron.utils import OneHotSwitch
+from transactron.utils.fifo import BasicFifo
 from coreblocks.utils.protocols import FuncUnit
 from coreblocks.fu.division.long_division import LongDivider
 

coreblocks/fu/exception.py

@@ -7,7 +7,7 @@
 from transactron.lib import FIFO
 
 from coreblocks.params import OpType, GenParams, FuncUnitLayouts, FunctionalComponentParams
-from coreblocks.utils import OneHotSwitch
+from transactron.utils import OneHotSwitch
 from coreblocks.params.keys import ExceptionReportKey
 
 from coreblocks.fu.fu_decoder import DecoderManager

coreblocks/fu/jumpbranch.py

@@ -9,7 +9,7 @@
 from transactron.lib import *
 
 from coreblocks.params import *
-from coreblocks.utils import OneHotSwitch
+from transactron.utils import OneHotSwitch
 from coreblocks.utils.protocols import FuncUnit
 
 from coreblocks.fu.fu_decoder import DecoderManager

coreblocks/fu/mul_unit.py

@@ -18,7 +18,7 @@
 
 __all__ = ["MulUnit", "MulFn", "MulComponent", "MulType"]
 
-from coreblocks.utils import OneHotSwitch
+from transactron.utils import OneHotSwitch
 from coreblocks.utils.protocols import FuncUnit
 
 

coreblocks/fu/shift_unit.py

@@ -5,7 +5,7 @@
 from transactron.lib import FIFO
 
 from coreblocks.params import OpType, Funct3, Funct7, GenParams, FuncUnitLayouts, FunctionalComponentParams
-from coreblocks.utils import OneHotSwitch
+from transactron.utils import OneHotSwitch
 
 from coreblocks.fu.fu_decoder import DecoderManager
 from enum import IntFlag, auto

coreblocks/fu/zbc.py

@@ -14,7 +14,7 @@
 )
 from transactron import Method, def_method, TModule
 from transactron.lib import FIFO
-from coreblocks.utils import OneHotSwitch
+from transactron.utils import OneHotSwitch
 from coreblocks.utils.protocols import FuncUnit
 
 

coreblocks/fu/zbs.py

@@ -5,7 +5,7 @@
 from coreblocks.params import Funct3, GenParams, FuncUnitLayouts, OpType, Funct7, FunctionalComponentParams
 from transactron import Method, TModule, def_method
 from transactron.lib import FIFO
-from coreblocks.utils import OneHotSwitch
+from transactron.utils import OneHotSwitch
 from coreblocks.utils.protocols import FuncUnit
 
 from coreblocks.fu.fu_decoder import DecoderManager

coreblocks/lsu/dummyLsu.py

@@ -3,7 +3,7 @@
 from transactron import Method, def_method, Transaction, TModule
 from coreblocks.params import *
 from coreblocks.peripherals.wishbone import WishboneMaster
-from coreblocks.utils import assign, ModuleLike
+from transactron.utils import assign, ModuleLike
 from coreblocks.utils.protocols import FuncBlock
 
 

coreblocks/params/instr.py

@@ -3,7 +3,7 @@
 from amaranth.hdl.ast import ValueCastable
 from amaranth import *
 
-from coreblocks.utils import ValueLike
+from transactron.utils import ValueLike
 from coreblocks.params.isa import *
 
 

coreblocks/params/layouts.py

@@ -1,6 +1,6 @@
 from coreblocks.params import GenParams, OpType, Funct7, Funct3
 from coreblocks.params.isa import ExceptionCause
-from coreblocks.utils.utils import layout_subset
+from transactron.utils.utils import layout_subset
 
 __all__ = [
     "SchedulerLayouts",

coreblocks/peripherals/wishbone.py

@@ -7,8 +7,8 @@
 
 from transactron import Method, def_method, TModule
 from transactron.lib import AdapterTrans
-from coreblocks.utils.utils import OneHotSwitchDynamic, assign
-from coreblocks.utils.fifo import BasicFifo
+from transactron.utils.utils import OneHotSwitchDynamic, assign
+from transactron.utils.fifo import BasicFifo
 
 
 class WishboneParameters:

coreblocks/scheduler/scheduler.py

@@ -5,7 +5,7 @@
 from transactron import Method, Transaction, TModule
 from transactron.lib import FIFO, Forwarder
 from coreblocks.params import SchedulerLayouts, GenParams, OpType
-from coreblocks.utils import assign, AssignType
+from transactron.utils import assign, AssignType
 from coreblocks.utils.protocols import FuncBlock
 
 

coreblocks/scheduler/wakeup_select.py

@@ -1,7 +1,7 @@
 from amaranth import *
 
 from coreblocks.params import GenParams, FuncUnitLayouts
-from coreblocks.utils import assign, AssignType
+from transactron.utils import assign, AssignType
 from transactron.core import *
 
 __all__ = ["WakeupSelect"]

coreblocks/structs_common/csr.py

@@ -3,7 +3,7 @@
 from dataclasses import dataclass
 
 from transactron import Method, def_method, Transaction, TModule
-from coreblocks.utils import assign, bits_from_int
+from transactron.utils import assign, bits_from_int
 from coreblocks.params.genparams import GenParams
 from coreblocks.params.dependencies import DependencyManager, ListKey
 from coreblocks.params.fu_params import BlockComponentParams

coreblocks/utils/__init__.py

@@ -1,3 +0,0 @@
-from .utils import *  # noqa: F401
-from ._typing import *  # noqa: F401
-from .debug_signals import *  # noqa: F401

coreblocks/utils/protocols.py

@@ -1,6 +1,6 @@
 from typing import Protocol
 from transactron import Method
-from ._typing import HasElaborate
+from transactron.utils._typing import HasElaborate
 
 
 __all__ = ["FuncUnit", "FuncBlock", "Unifier"]

scripts/gen_verilog.py

@@ -16,7 +16,7 @@
 from coreblocks.peripherals.wishbone import WishboneBus
 from coreblocks.core import Core
 from transactron import TransactionModule
-from coreblocks.utils.utils import flatten_signals
+from transactron.utils.utils import flatten_signals
 
 from coreblocks.params.configurations import *
 

scripts/synthesize.py

@@ -13,7 +13,7 @@
     sys.path.insert(0, parent)
 
 
-from coreblocks.utils.utils import ModuleConnector
+from transactron.utils.utils import ModuleConnector
 from coreblocks.params.genparams import GenParams
 from coreblocks.params.fu_params import FunctionalComponentParams
 from coreblocks.core import Core

test/common/functions.py

@@ -2,7 +2,7 @@
 from amaranth.hdl.ast import Statement
 from amaranth.sim.core import Command
 from typing import TypeVar, Any, Generator, TypeAlias
-from coreblocks.utils._typing import RecordValueDict, RecordIntDict
+from transactron.utils._typing import RecordValueDict, RecordIntDict
 
 T = TypeVar("T")
 TestGen: TypeAlias = Generator[Command | Value | Statement | None, Any, T]

test/common/infrastructure.py

@@ -11,7 +11,7 @@
 from transactron import Method
 from transactron.lib import AdapterTrans
 from transactron.core import TransactionModule
-from coreblocks.utils import ModuleConnector, HasElaborate, auto_debug_signals, HasDebugSignals
+from transactron.utils import ModuleConnector, HasElaborate, auto_debug_signals, HasDebugSignals
 
 T = TypeVar("T")
 _T_nested_collection = T | list["_T_nested_collection[T]"] | dict[str, "_T_nested_collection[T]"]

test/common/sugar.py

@@ -1,7 +1,7 @@
 import functools
 from typing import Callable, Any, Optional
 from .testbenchio import TestbenchIO, TestGen
-from coreblocks.utils._typing import RecordIntDict
+from transactron.utils._typing import RecordIntDict
 
 
 def def_method_mock(

test/common/testbenchio.py

@@ -4,7 +4,7 @@
 from transactron.lib import AdapterBase
 from transactron.core import ValueLike, SignalBundle
 from transactron._utils import mock_def_helper
-from coreblocks.utils._typing import RecordIntDictRet, RecordValueDict, RecordIntDict
+from transactron.utils._typing import RecordIntDictRet, RecordValueDict, RecordIntDict
 from .functions import set_inputs, get_outputs, TestGen
 
 

test/frontend/test_fetch.py

@@ -11,7 +11,7 @@
 from coreblocks.frontend.icache import ICacheInterface
 from coreblocks.params import *
 from coreblocks.params.configurations import test_core_config
-from coreblocks.utils import ModuleConnector
+from transactron.utils import ModuleConnector
 from ..common import TestCaseWithSimulator, TestbenchIO, def_method_mock
 
 

test/frontend/test_rvc.py

@@ -6,7 +6,7 @@
 from coreblocks.frontend.rvc import InstrDecompress
 from coreblocks.params import *
 from coreblocks.params.configurations import test_core_config
-from coreblocks.utils import ValueLike
+from transactron.utils import ValueLike
 
 from ..common import TestCaseWithSimulator
 

test/gtkw_extension.py

@@ -2,7 +2,7 @@
 from contextlib import contextmanager
 from amaranth.sim.pysim import _VCDWriter
 from amaranth import *
-from coreblocks.utils.utils import flatten_signals
+from transactron.utils.utils import flatten_signals
 
 
 class _VCDWriterExt(_VCDWriter):

test/regression/memory.py

@@ -6,7 +6,7 @@
 from elftools.elf.constants import P_FLAGS
 from elftools.elf.elffile import ELFFile, Segment
 from coreblocks.params.configurations import CoreConfiguration
-from coreblocks.utils.utils import align_to_power_of_two, align_down_to_power_of_two
+from transactron.utils.utils import align_to_power_of_two, align_down_to_power_of_two
 
 all = [
     "ReplyStatus",

test/structs_common/test_exception.py

@@ -6,7 +6,7 @@
 from coreblocks.params.isa import ExceptionCause
 from coreblocks.params.configurations import test_core_config
 from transactron.lib import Adapter
-from coreblocks.utils.utils import ModuleConnector
+from transactron.utils.utils import ModuleConnector
 
 from ..common import *
 

test/test_core.py

@@ -1,7 +1,7 @@
 from amaranth import Elaboratable, Module
 
 from transactron.lib import AdapterTrans
-from coreblocks.utils import align_to_power_of_two
+from transactron.utils import align_to_power_of_two
 
 from .common import TestCaseWithSimulator, TestbenchIO
 

test/transactions/test_assign.py

@@ -3,8 +3,8 @@
 from amaranth.lib import data
 from amaranth.hdl.ast import ArrayProxy, Slice
 
-from coreblocks.utils._typing import LayoutLike
-from coreblocks.utils.utils import AssignArg, AssignType, AssignFields, assign
+from transactron.utils._typing import LayoutLike
+from transactron.utils.utils import AssignArg, AssignType, AssignFields, assign
 
 from unittest import TestCase
 from parameterized import parameterized_class, parameterized

test/transactions/test_simultaneous.py

@@ -3,7 +3,7 @@
 from amaranth import *
 from amaranth.sim import *
 
-from coreblocks.utils.utils import ModuleConnector
+from transactron.utils.utils import ModuleConnector
 
 from ..common import SimpleTestCircuit, TestCaseWithSimulator, TestbenchIO, def_method_mock
 

test/transactions/test_transaction_lib.py

@@ -13,8 +13,8 @@
 from transactron.core import RecordDict
 from transactron.lib import *
 from coreblocks.utils import *
-from coreblocks.utils._typing import LayoutLike, ModuleLike
-from coreblocks.utils import ModuleConnector
+from transactron.utils._typing import LayoutLike, ModuleLike
+from transactron.utils import ModuleConnector
 from ..common import (
     SimpleTestCircuit,
     TestCaseWithSimulator,

test/utils/test_fifo.py

@@ -1,6 +1,6 @@
 from amaranth import *
 
-from coreblocks.utils.fifo import BasicFifo
+from transactron.utils.fifo import BasicFifo
 from transactron.lib import AdapterTrans
 
 from test.common import TestCaseWithSimulator, TestbenchIO, data_layout

test/utils/test_onehotswitch.py

@@ -1,7 +1,7 @@
 from amaranth import *
 from amaranth.sim import *
 
-from coreblocks.utils import OneHotSwitch
+from transactron.utils import OneHotSwitch
 
 from test.common import TestCaseWithSimulator
 

test/utils/test_utils.py

@@ -3,7 +3,7 @@
 
 from amaranth import *
 from test.common import *
-from coreblocks.utils import (
+from transactron.utils import (
     align_to_power_of_two,
     align_down_to_power_of_two,
     popcount,

transactron/_utils.py

@@ -4,8 +4,8 @@
 from typing import Any, Concatenate, Optional, TypeAlias, TypeGuard, TypeVar
 from collections.abc import Callable, Iterable, Mapping
 from amaranth import *
-from coreblocks.utils._typing import LayoutLike, ShapeLike
-from coreblocks.utils import OneHotSwitchDynamic
+from transactron.utils._typing import LayoutLike, ShapeLike
+from transactron.utils import OneHotSwitchDynamic
 
 __all__ = [
     "Scheduler",

transactron/core.py

@@ -21,11 +21,10 @@
 from itertools import count, chain, filterfalse, product
 from amaranth.hdl.dsl import FSM, _ModuleBuilderDomain
 
-from coreblocks.utils import AssignType, assign, ModuleConnector
-from coreblocks.utils.utils import OneHotSwitchDynamic
+from transactron.utils import AssignType, assign, ModuleConnector, silence_mustuse
+from transactron.utils.utils import OneHotSwitchDynamic
 from ._utils import *
-from coreblocks.utils import silence_mustuse
-from coreblocks.utils._typing import ValueLike, SignalBundle, HasElaborate, SwitchKey, ModuleLike
+from transactron.utils._typing import ValueLike, SignalBundle, HasElaborate, SwitchKey, ModuleLike
 from .graph import Owned, OwnershipGraph, Direction
 
 __all__ = [

transactron/lib/reqres.py

@@ -1,7 +1,7 @@
 from amaranth import *
 from ..core import *
 from .connectors import Forwarder, FIFO
-from coreblocks.utils.fifo import BasicFifo
+from transactron.utils.fifo import BasicFifo
 from amaranth.utils import *
 
 __all__ = [