Use requirements.txt in core synthesis

.github/workflows/main.yml

@@ -30,7 +30,7 @@ jobs:
           python3 -m venv venv
           . venv/bin/activate
           python3 -m pip install --upgrade pip
-          python3 -m pip install -r requirements-dev.txt
+          python3 -m pip install -r requirements.txt
 
       - name: Generate Verilog
         run: |