Allow parallel compilation of the verilated model

kuznia-rdzeni · Mar 21, 2024 · 5074fbc · 5074fbc
1 parent 044b125
commit 5074fbc
Show file tree

Hide file tree

Showing 3 changed files with 3 additions and 0 deletions.
diff --git a/test/regression/cocotb/benchmark.Makefile b/test/regression/cocotb/benchmark.Makefile
@@ -15,6 +15,7 @@ SIM_BUILD = build/benchmark
 # Yosys/Amaranth borkedness workaround
 ifeq ($(SIM),verilator)
   EXTRA_ARGS += -Wno-CASEINCOMPLETE -Wno-CASEOVERLAP -Wno-WIDTHEXPAND -Wno-WIDTHTRUNC
+  BUILD_ARGS += -j`nproc`
 endif
 
 ifeq ($(TRACES),1)

diff --git a/test/regression/cocotb/signature.Makefile b/test/regression/cocotb/signature.Makefile
@@ -15,6 +15,7 @@ SIM_BUILD = build/signature
 # Yosys/Amaranth borkedness workaround
 ifeq ($(SIM),verilator)
   EXTRA_ARGS += -Wno-CASEINCOMPLETE -Wno-CASEOVERLAP -Wno-WIDTHEXPAND -Wno-WIDTHTRUNC
+  BUILD_ARGS += -j`nproc`
 endif
 
 ifeq ($(TRACES),1)

diff --git a/test/regression/cocotb/test.Makefile b/test/regression/cocotb/test.Makefile
@@ -15,6 +15,7 @@ SIM_BUILD = build/test
 # Yosys/Amaranth borkedness workaround
 ifeq ($(SIM),verilator)
   EXTRA_ARGS += -Wno-CASEINCOMPLETE -Wno-CASEOVERLAP -Wno-WIDTHEXPAND -Wno-WIDTHTRUNC
+  BUILD_ARGS += -j`nproc`
 endif
 
 ifeq ($(TRACES),1)