Merge branch 'master' into tilk/actions-node-20

coreblocks/stages/retirement.py → coreblocks/backend/retirement.py

@@ -1,15 +1,15 @@
 from amaranth import *
-from coreblocks.params.layouts import RetirementLayouts
+from coreblocks.interface.layouts import RetirementLayouts
 
 from transactron.core import Method, Transaction, TModule, def_method
 from transactron.lib.simultaneous import condition
 from transactron.utils.dependencies import DependencyManager
 from transactron.lib.metrics import *
 
 from coreblocks.params.genparams import GenParams
-from coreblocks.params.isa import ExceptionCause
-from coreblocks.params.keys import CoreStateKey, GenericCSRRegistersKey
-from coreblocks.structs_common.csr_generic import CSRAddress, DoubleCounterCSR
+from coreblocks.frontend.decoder.isa import ExceptionCause
+from coreblocks.interface.keys import CoreStateKey, GenericCSRRegistersKey
+from coreblocks.priv.csr.csr_instances import CSRAddress, DoubleCounterCSR
 
 
 class Retirement(Elaboratable):

coreblocks/cache/icache.py

@@ -7,7 +7,8 @@
 
 from transactron.core import def_method, Priority, TModule
 from transactron import Method, Transaction
-from coreblocks.params import ICacheLayouts, ICacheParameters
+from coreblocks.params import ICacheParameters
+from coreblocks.interface.layouts import ICacheLayouts
 from transactron.utils import assign, OneHotSwitchDynamic
 from transactron.lib import *
 from coreblocks.peripherals.bus_adapter import BusMasterInterface

coreblocks/cache/refiller.py

@@ -1,6 +1,7 @@
 from amaranth import *
 from coreblocks.cache.icache import CacheRefillerInterface
-from coreblocks.params import ICacheLayouts, ICacheParameters
+from coreblocks.params import ICacheParameters
+from coreblocks.interface.layouts import ICacheLayouts
 from coreblocks.peripherals.bus_adapter import BusMasterInterface
 from transactron.core import Transaction
 from transactron.lib import Forwarder, Method, TModule, def_method

coreblocks/core.py

@@ -2,35 +2,35 @@
 from amaranth.lib.wiring import flipped, connect
 
 from transactron.utils.dependencies import DependencyManager, DependencyContext
-from coreblocks.stages.func_blocks_unifier import FuncBlocksUnifier
-from coreblocks.structs_common.instr_counter import CoreInstructionCounter
-from coreblocks.structs_common.interrupt_controller import InterruptController
+from coreblocks.func_blocks.interface.func_blocks_unifier import FuncBlocksUnifier
+from coreblocks.priv.traps.instr_counter import CoreInstructionCounter
+from coreblocks.priv.traps.interrupt_controller import InterruptController
 from transactron.core import Transaction, TModule
 from transactron.lib import FIFO, ConnectTrans
-from coreblocks.params.layouts import *
-from coreblocks.params.keys import (
+from coreblocks.interface.layouts import *
+from coreblocks.interface.keys import (
     BranchVerifyKey,
     FetchResumeKey,
     GenericCSRRegistersKey,
     InstructionPrecommitKey,
     CommonBusDataKey,
 )
 from coreblocks.params.genparams import GenParams
-from coreblocks.params.isa import Extension
-from coreblocks.frontend.decode_stage import DecodeStage
-from coreblocks.structs_common.rat import FRAT, RRAT
-from coreblocks.structs_common.rob import ReorderBuffer
-from coreblocks.structs_common.rf import RegisterFile
-from coreblocks.structs_common.csr_generic import GenericCSRRegisters
-from coreblocks.structs_common.exception import ExceptionCauseRegister
+from coreblocks.params.isa_params import Extension
+from coreblocks.frontend.decoder.decode_stage import DecodeStage
+from coreblocks.core_structs.rat import FRAT, RRAT
+from coreblocks.core_structs.rob import ReorderBuffer
+from coreblocks.core_structs.rf import RegisterFile
+from coreblocks.priv.csr.csr_instances import GenericCSRRegisters
+from coreblocks.priv.traps.exception import ExceptionCauseRegister
 from coreblocks.scheduler.scheduler import Scheduler
-from coreblocks.stages.backend import ResultAnnouncement
-from coreblocks.stages.retirement import Retirement
+from coreblocks.backend.annoucement import ResultAnnouncement
+from coreblocks.backend.retirement import Retirement
 from coreblocks.cache.icache import ICache, ICacheBypass
 from coreblocks.peripherals.bus_adapter import WishboneMasterAdapter
 from coreblocks.peripherals.wishbone import WishboneMaster, WishboneInterface
 from coreblocks.cache.refiller import SimpleCommonBusCacheRefiller
-from coreblocks.frontend.fetch import Fetch, UnalignedFetch
+from coreblocks.frontend.fetch.fetch import Fetch, UnalignedFetch
 from transactron.lib.transformers import MethodMap, MethodProduct
 from transactron.lib import BasicFifo
 from transactron.lib.metrics import HwMetricsEnabledKey

coreblocks/structs_common/rat.py → coreblocks/core_structs/rat.py

@@ -1,6 +1,7 @@
 from amaranth import *
 from transactron import Method, def_method, TModule
-from coreblocks.params import RATLayouts, GenParams
+from coreblocks.interface.layouts import RATLayouts
+from coreblocks.params import GenParams
 
 __all__ = ["FRAT", "RRAT"]
 

coreblocks/structs_common/rf.py → coreblocks/core_structs/rf.py

@@ -1,6 +1,7 @@
 from amaranth import *
 from transactron import Method, def_method, TModule
-from coreblocks.params import RFLayouts, GenParams
+from coreblocks.interface.layouts import RFLayouts
+from coreblocks.params import GenParams
 from transactron.utils.transactron_helpers import make_layout
 
 __all__ = ["RegisterFile"]

coreblocks/structs_common/rob.py → coreblocks/core_structs/rob.py

@@ -1,7 +1,8 @@
 from amaranth import *
 from transactron import Method, def_method, TModule
 from transactron.lib.metrics import *
-from ..params import GenParams, ROBLayouts
+from coreblocks.interface.layouts import ROBLayouts
+from coreblocks.params import GenParams
 
 __all__ = ["ReorderBuffer"]
 

coreblocks/frontend/decoder/__init__.py

@@ -0,0 +1,2 @@
+from .isa import *  # noqa: F401
+from .optypes import *  # noqa: F401

coreblocks/frontend/decode_stage.py → coreblocks/frontend/decoder/decode_stage.py

@@ -1,10 +1,10 @@
 from amaranth import *
 
-from coreblocks.params.isa import Funct3
-from coreblocks.params.optypes import OpType
+from coreblocks.frontend.decoder.isa import Funct3
+from coreblocks.frontend.decoder.optypes import OpType
 from transactron.lib.metrics import *
 from transactron import Method, Transaction, TModule
-from ..params import GenParams
+from coreblocks.params import GenParams
 from .instr_decoder import InstrDecoder
 from coreblocks.params import *
 

coreblocks/frontend/instr_decoder.py → coreblocks/frontend/decoder/instr_decoder.py

@@ -4,6 +4,8 @@
 from amaranth import *
 
 from coreblocks.params import *
+from coreblocks.frontend.decoder.optypes import *
+from coreblocks.frontend.decoder.isa import *
 from .instr_description import instructions_by_optype, Encoding
 
 __all__ = ["InstrDecoder"]

coreblocks/frontend/instr_description.py → coreblocks/frontend/decoder/instr_description.py

@@ -2,6 +2,8 @@
 from typing import Optional
 
 from coreblocks.params import *
+from .isa import *
+from .optypes import *
 
 
 @dataclass(frozen=True)

coreblocks/frontend/decoder/isa.py

@@ -0,0 +1,154 @@
+from amaranth.lib.enum import unique, Enum, IntEnum, IntFlag
+
+__all__ = [
+    "InstrType",
+    "Opcode",
+    "Funct3",
+    "Funct7",
+    "Funct12",
+    "ExceptionCause",
+    "FenceTarget",
+    "FenceFm",
+    "Registers",
+]
+
+
+@unique
+class InstrType(Enum):
+    R = 0
+    I = 1  # noqa: E741
+    S = 2
+    B = 3
+    U = 4
+    J = 5
+
+
+@unique
+class Opcode(IntEnum, shape=5):
+    LOAD = 0b00000
+    LOAD_FP = 0b00001
+    MISC_MEM = 0b00011
+    OP_IMM = 0b00100
+    AUIPC = 0b00101
+    OP_IMM_32 = 0b00110
+    STORE = 0b01000
+    STORE_FP = 0b01001
+    OP = 0b01100
+    LUI = 0b01101
+    OP32 = 0b01110
+    BRANCH = 0b11000
+    JALR = 0b11001
+    JAL = 0b11011
+    SYSTEM = 0b11100
+
+
+class Funct3(IntEnum, shape=3):
+    JALR = BEQ = B = ADD = SUB = FENCE = PRIV = MUL = MULW = _EINSTRACCESSFAULT = 0b000
+    BNE = H = SLL = FENCEI = CSRRW = MULH = BCLR = BINV = BSET = CLZ = CPOP = CTZ = ROL \
+            = SEXTB = SEXTH = CLMUL = _EILLEGALINSTR = 0b001  # fmt: skip
+    W = SLT = CSRRS = MULHSU = SH1ADD = CLMULR = _EBREAKPOINT = 0b010
+    D = SLTU = CSRRC = MULHU = CLMULH = _EINSTRPAGEFAULT = 0b011
+    BLT = BU = XOR = DIV = DIVW = SH2ADD = MIN = XNOR = ZEXTH = 0b100
+    BGE = HU = SR = CSRRWI = DIVU = DIVUW = BEXT = ORCB = REV8 = ROR = MINU = 0b101
+    BLTU = OR = CSRRSI = REM = REMW = SH3ADD = MAX = ORN = 0b110
+    BGEU = AND = CSRRCI = REMU = REMUW = ANDN = MAXU = 0b111
+
+
+class Funct7(IntEnum, shape=7):
+    SL = SLT = ADD = XOR = OR = AND = 0b0000000
+    SA = SUB = ANDN = ORN = XNOR = 0b0100000
+    MULDIV = 0b0000001
+    SH1ADD = SH2ADD = SH3ADD = 0b0010000
+    BCLR = BEXT = 0b0100100
+    BINV = REV8 = 0b0110100
+    BSET = ORCB = 0b0010100
+    MAX = MIN = CLMUL = 0b0000101
+    ROL = ROR = SEXTB = SEXTH = CPOP = CLZ = CTZ = 0b0110000
+    ZEXTH = 0b0000100
+    SFENCEVMA = 0b0001001
+
+
+class Funct12(IntEnum, shape=12):
+    ECALL = 0b000000000000
+    EBREAK = 0b000000000001
+    SRET = 0b000100000010
+    MRET = 0b001100000010
+    WFI = 0b000100000101
+    CPOP = 0b011000000010
+    CLZ = 0b011000000000
+    CTZ = 0b011000000001
+    ORCB = 0b001010000111
+    REV8_32 = 0b011010011000
+    REV8_64 = 0b011010111000
+    SEXTB = 0b011000000100
+    SEXTH = 0b011000000101
+    ZEXTH = 0b000010000000
+
+
+class Registers(IntEnum, shape=5):
+    X0 = ZERO = 0b00000  # hardwired zero
+    X1 = RA = 0b00001  # return address
+    X2 = SP = 0b00010  # stack pointer
+    X3 = GP = 0b00011  # global pointer
+    X4 = TP = 0b00100  # thread pointer
+    X5 = T0 = 0b00101  # temporary register 0
+    X6 = T1 = 0b00110  # temporary register 1
+    X7 = T2 = 0b00111  # temporary register 2
+    X8 = S0 = FP = 0b01000  # saved register 0 / frame pointer
+    X9 = S1 = 0b01001  # saved register 1
+    X10 = A0 = 0b01010  # function argument 0 / return value 0
+    X11 = A1 = 0b01011  # function argument 1 / return value 1
+    X12 = A2 = 0b01100  # function argument 2
+    X13 = A3 = 0b01101  # function argument 3
+    X14 = A4 = 0b01110  # function argument 4
+    X15 = A5 = 0b01111  # function argument 5
+    X16 = A6 = 0b10000  # function argument 6
+    X17 = A7 = 0b10001  # function argument 7
+    X18 = S2 = 0b10010  # saved register 2
+    X19 = S3 = 0b10011  # saved register 3
+    X20 = S4 = 0b10100  # saved register 4
+    X21 = S5 = 0b10101  # saved register 5
+    X22 = S6 = 0b10110  # saved register 6
+    X23 = S7 = 0b10111  # saved register 7
+    X24 = S8 = 0b11000  # saved register 8
+    X25 = S9 = 0b11001  # saved register 9
+    X26 = S10 = 0b11010  # saved register 10
+    X27 = S11 = 0b11011  # saved register 11
+    X28 = T3 = 0b11100  # temporary register 3
+    X29 = T4 = 0b11101  # temporary register 4
+    X30 = T5 = 0b11110  # temporary register 5
+    X31 = T6 = 0b11111  # temporary register 6
+
+
+@unique
+class FenceTarget(IntFlag, shape=4):
+    MEM_W = 0b0001
+    MEM_R = 0b0010
+    DEV_O = 0b0100
+    DEV_I = 0b1000
+
+
+@unique
+class FenceFm(IntEnum, shape=4):
+    NONE = 0b0000
+    TSO = 0b1000
+
+
+@unique
+class ExceptionCause(IntEnum, shape=5):
+    INSTRUCTION_ADDRESS_MISALIGNED = 0
+    INSTRUCTION_ACCESS_FAULT = 1
+    ILLEGAL_INSTRUCTION = 2
+    BREAKPOINT = 3
+    LOAD_ADDRESS_MISALIGNED = 4
+    LOAD_ACCESS_FAULT = 5
+    STORE_ADDRESS_MISALIGNED = 6
+    STORE_ACCESS_FAULT = 7
+    ENVIRONMENT_CALL_FROM_U = 8
+    ENVIRONMENT_CALL_FROM_S = 9
+    ENVIRONMENT_CALL_FROM_M = 11
+    INSTRUCTION_PAGE_FAULT = 12
+    LOAD_PAGE_FAULT = 13
+    STORE_PAGE_FAULT = 15
+    _COREBLOCKS_ASYNC_INTERRUPT = 16
+    _COREBLOCKS_MISPREDICTION = 17

coreblocks/params/optypes.py → coreblocks/frontend/decoder/optypes.py

@@ -1,7 +1,7 @@
 from enum import IntEnum, auto, unique
 
 from coreblocks.params import Extension
-from coreblocks.params.isa import extension_implications, extension_only_implies
+from coreblocks.params.isa_params import extension_implications, extension_only_implies
 
 
 @unique

coreblocks/frontend/rvc.py → coreblocks/frontend/decoder/rvc.py

@@ -2,6 +2,7 @@
 
 from transactron import TModule
 from coreblocks.params import *
+from coreblocks.frontend.decoder.isa import *
 from transactron.utils import ValueLike
 
 

coreblocks/frontend/fetch.py → coreblocks/frontend/fetch/fetch.py

@@ -3,9 +3,11 @@
 from transactron.lib import BasicFifo, Semaphore
 from transactron.lib.metrics import *
 from coreblocks.cache.iface import CacheInterface
-from coreblocks.frontend.rvc import InstrDecompress, is_instr_compressed
+from coreblocks.frontend.decoder.rvc import InstrDecompress, is_instr_compressed
 from transactron import def_method, Method, Transaction, TModule
-from ..params import *
+from coreblocks.params import *
+from coreblocks.interface.layouts import *
+from coreblocks.frontend.decoder.isa import *
 
 
 class Fetch(Elaboratable):