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Merge branch 'master' into sorting_network
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Jacob Urbanczyk committed Mar 25, 2024
2 parents afd2a42 + 6128533 commit 469c3dc
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14 changes: 7 additions & 7 deletions .github/workflows/benchmark.yml
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Expand Up @@ -16,15 +16,15 @@ jobs:
timeout-minutes: 40
container: ghcr.io/kuznia-rdzeni/amaranth-synth:ecp5-2023.11.19_v
steps:
- uses: actions/checkout@v3
- uses: actions/checkout@v4

- name: Set ownership (Github Actions workaround)
run: |
# https://github.com/actions/runner/issues/2033
chown -R $(id -u):$(id -g) $PWD
- name: Set up Python
uses: actions/setup-python@v4
uses: actions/setup-python@v5
with:
python-version: '3.11'

Expand Down Expand Up @@ -66,14 +66,14 @@ jobs:
container: ghcr.io/kuznia-rdzeni/riscv-toolchain:2024.03.12
steps:
- name: Checkout
uses: actions/checkout@v3
uses: actions/checkout@v4
with:
submodules: recursive

- name: Build embench
run: cd test/external/embench && make

- uses: actions/upload-artifact@v3
- uses: actions/upload-artifact@v4
with:
name: "embench"
path: |
Expand All @@ -87,15 +87,15 @@ jobs:
needs: build-perf-benchmarks
steps:
- name: Checkout
uses: actions/checkout@v3
uses: actions/checkout@v4

- name: Set ownership (Github Actions workaround)
run: |
# https://github.com/actions/runner/issues/2033
chown -R $(id -u):$(id -g) $PWD
- name: Set up Python
uses: actions/setup-python@v4
uses: actions/setup-python@v5
with:
python-version: '3.11'

Expand All @@ -111,7 +111,7 @@ jobs:
. venv/bin/activate
PYTHONHASHSEED=0 TRANSACTRON_VERBOSE=1 ./scripts/gen_verilog.py --verbose --config full
- uses: actions/download-artifact@v3
- uses: actions/download-artifact@v4
with:
name: "embench"
path: test/external/embench/build
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4 changes: 2 additions & 2 deletions .github/workflows/deploy_gh_pages.yml
Original file line number Diff line number Diff line change
Expand Up @@ -21,10 +21,10 @@ jobs:
BUILD_DIR: "build"
steps:
- name: Checkout
uses: actions/checkout@v3
uses: actions/checkout@v4

- name: Set up Python
uses: actions/setup-python@v4
uses: actions/setup-python@v5
with:
python-version: "3.11"

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46 changes: 23 additions & 23 deletions .github/workflows/main.yml
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Expand Up @@ -18,10 +18,10 @@ jobs:
timeout-minutes: 5
steps:
- name: Checkout
uses: actions/checkout@v3
uses: actions/checkout@v4

- name: Set up Python
uses: actions/setup-python@v4
uses: actions/setup-python@v5
with:
python-version: '3.11'

Expand All @@ -37,7 +37,7 @@ jobs:
. venv/bin/activate
PYTHONHASHSEED=0 TRANSACTRON_VERBOSE=1 ./scripts/gen_verilog.py --verbose --config full
- uses: actions/upload-artifact@v3
- uses: actions/upload-artifact@v4
with:
name: "verilog-full-core"
path: |
Expand All @@ -60,7 +60,7 @@ jobs:

steps:
- name: Checkout
uses: actions/checkout@v3
uses: actions/checkout@v4

- name: Get submodules HEAD hash
working-directory: .
Expand All @@ -72,7 +72,7 @@ jobs:
- name: Cache compiled and reference riscv-arch-test
id: cache-riscv-arch-test
uses: actions/cache@v3
uses: actions/cache@v4
env:
cache-name: cache-riscv-arch-test
with:
Expand All @@ -93,7 +93,7 @@ jobs:

- if: ${{ steps.cache-riscv-arch-test.outputs.cache-hit != 'true' }}
name: Checkout with submodules
uses: actions/checkout@v3
uses: actions/checkout@v4
with:
submodules: recursive

Expand Down Expand Up @@ -127,7 +127,7 @@ jobs:
- if: ${{ steps.cache-riscv-arch-test.outputs.cache-hit != 'true' }}
name: Upload compiled and reference tests artifact
uses: actions/upload-artifact@v3
uses: actions/upload-artifact@v4
with:
name: "riscof-tests"
path: |
Expand All @@ -143,10 +143,10 @@ jobs:
timeout-minutes: 30
steps:
- name: Checkout
uses: actions/checkout@v3
uses: actions/checkout@v4

- name: Set up Python
uses: actions/setup-python@v4
uses: actions/setup-python@v5
with:
python-version: '3.11'

Expand All @@ -157,7 +157,7 @@ jobs:
python3 -m pip install --upgrade pip
python3 -m pip install -r requirements-dev.txt
- uses: actions/download-artifact@v3
- uses: actions/download-artifact@v4
name: Download full verilog core
with:
name: "verilog-full-core"
Expand All @@ -168,7 +168,7 @@ jobs:
git config --global --add safe.directory /__w/coreblocks/coreblocks
git submodule > .gitmodules-hash
- uses: actions/cache@v3
- uses: actions/cache@v4
name: Download tests from cache
env:
cache-name: cache-riscv-arch-test
Expand Down Expand Up @@ -204,7 +204,7 @@ jobs:
timeout-minutes: 10
steps:
- name: Checkout
uses: actions/checkout@v3
uses: actions/checkout@v4

- name: Get submodules HEAD hash
run: |
Expand All @@ -213,7 +213,7 @@ jobs:
- name: Cache regression-tests
id: cache-regression
uses: actions/cache@v3
uses: actions/cache@v4
env:
cache-name: cache-regression-tests
with:
Expand All @@ -229,7 +229,7 @@ jobs:

- if: ${{ steps.cache-regression.outputs.cache-hit != 'true' }}
name: Checkout with submodules
uses: actions/checkout@v3
uses: actions/checkout@v4
with:
submodules: recursive

Expand All @@ -238,7 +238,7 @@ jobs:

- if: ${{ steps.cache-regression.outputs.cache-hit != 'true' }}
name: Upload riscv-tests
uses: actions/upload-artifact@v3
uses: actions/upload-artifact@v4
with:
path: test/external/riscv-tests

Expand All @@ -250,10 +250,10 @@ jobs:
needs: [ build-regression-tests, build-core ]
steps:
- name: Checkout
uses: actions/checkout@v3
uses: actions/checkout@v4

- name: Set up Python
uses: actions/setup-python@v4
uses: actions/setup-python@v5
with:
python-version: '3.11'

Expand All @@ -264,7 +264,7 @@ jobs:
python3 -m pip install --upgrade pip
python3 -m pip install -r requirements-dev.txt
- uses: actions/download-artifact@v3
- uses: actions/download-artifact@v4
name: Download full verilog core
with:
name: "verilog-full-core"
Expand All @@ -275,7 +275,7 @@ jobs:
git config --global --add safe.directory /__w/coreblocks/coreblocks
git submodule > .gitmodules-hash
- uses: actions/cache@v3
- uses: actions/cache@v4
name: Download tests from cache
env:
cache-name: cache-regression-tests
Expand Down Expand Up @@ -307,10 +307,10 @@ jobs:
timeout-minutes: 15
steps:
- name: Checkout
uses: actions/checkout@v3
uses: actions/checkout@v4

- name: Set up Python
uses: actions/setup-python@v4
uses: actions/setup-python@v5
with:
python-version: '3.11'
cache: 'pip'
Expand Down Expand Up @@ -339,10 +339,10 @@ jobs:
timeout-minutes: 5
steps:
- name: Checkout
uses: actions/checkout@v3
uses: actions/checkout@v4

- name: Set up Python
uses: actions/setup-python@v4
uses: actions/setup-python@v5
with:
python-version: '3.11'
cache: 'pip'
Expand Down
File renamed without changes.
File renamed without changes.
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@@ -1,15 +1,15 @@
from amaranth import *
from coreblocks.params.layouts import RetirementLayouts
from coreblocks.interface.layouts import RetirementLayouts

from transactron.core import Method, Transaction, TModule, def_method
from transactron.lib.simultaneous import condition
from transactron.utils.dependencies import DependencyManager
from transactron.lib.metrics import *

from coreblocks.params.genparams import GenParams
from coreblocks.params.isa import ExceptionCause
from coreblocks.params.keys import CoreStateKey, GenericCSRRegistersKey
from coreblocks.structs_common.csr_generic import CSRAddress, DoubleCounterCSR
from coreblocks.frontend.decoder.isa import ExceptionCause
from coreblocks.interface.keys import CoreStateKey, GenericCSRRegistersKey
from coreblocks.priv.csr.csr_instances import CSRAddress, DoubleCounterCSR


class Retirement(Elaboratable):
Expand Down
3 changes: 2 additions & 1 deletion coreblocks/cache/icache.py
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,8 @@

from transactron.core import def_method, Priority, TModule
from transactron import Method, Transaction
from coreblocks.params import ICacheLayouts, ICacheParameters
from coreblocks.params import ICacheParameters
from coreblocks.interface.layouts import ICacheLayouts
from transactron.utils import assign, OneHotSwitchDynamic
from transactron.lib import *
from coreblocks.peripherals.bus_adapter import BusMasterInterface
Expand Down
3 changes: 2 additions & 1 deletion coreblocks/cache/refiller.py
Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
from amaranth import *
from coreblocks.cache.icache import CacheRefillerInterface
from coreblocks.params import ICacheLayouts, ICacheParameters
from coreblocks.params import ICacheParameters
from coreblocks.interface.layouts import ICacheLayouts
from coreblocks.peripherals.bus_adapter import BusMasterInterface
from transactron.core import Transaction
from transactron.lib import Forwarder, Method, TModule, def_method
Expand Down
30 changes: 15 additions & 15 deletions coreblocks/core.py
Original file line number Diff line number Diff line change
Expand Up @@ -2,35 +2,35 @@
from amaranth.lib.wiring import flipped, connect

from transactron.utils.dependencies import DependencyManager, DependencyContext
from coreblocks.stages.func_blocks_unifier import FuncBlocksUnifier
from coreblocks.structs_common.instr_counter import CoreInstructionCounter
from coreblocks.structs_common.interrupt_controller import InterruptController
from coreblocks.func_blocks.interface.func_blocks_unifier import FuncBlocksUnifier
from coreblocks.priv.traps.instr_counter import CoreInstructionCounter
from coreblocks.priv.traps.interrupt_controller import InterruptController
from transactron.core import Transaction, TModule
from transactron.lib import FIFO, ConnectTrans
from coreblocks.params.layouts import *
from coreblocks.params.keys import (
from coreblocks.interface.layouts import *
from coreblocks.interface.keys import (
BranchVerifyKey,
FetchResumeKey,
GenericCSRRegistersKey,
InstructionPrecommitKey,
CommonBusDataKey,
)
from coreblocks.params.genparams import GenParams
from coreblocks.params.isa import Extension
from coreblocks.frontend.decode_stage import DecodeStage
from coreblocks.structs_common.rat import FRAT, RRAT
from coreblocks.structs_common.rob import ReorderBuffer
from coreblocks.structs_common.rf import RegisterFile
from coreblocks.structs_common.csr_generic import GenericCSRRegisters
from coreblocks.structs_common.exception import ExceptionCauseRegister
from coreblocks.params.isa_params import Extension
from coreblocks.frontend.decoder.decode_stage import DecodeStage
from coreblocks.core_structs.rat import FRAT, RRAT
from coreblocks.core_structs.rob import ReorderBuffer
from coreblocks.core_structs.rf import RegisterFile
from coreblocks.priv.csr.csr_instances import GenericCSRRegisters
from coreblocks.priv.traps.exception import ExceptionCauseRegister
from coreblocks.scheduler.scheduler import Scheduler
from coreblocks.stages.backend import ResultAnnouncement
from coreblocks.stages.retirement import Retirement
from coreblocks.backend.annoucement import ResultAnnouncement
from coreblocks.backend.retirement import Retirement
from coreblocks.cache.icache import ICache, ICacheBypass
from coreblocks.peripherals.bus_adapter import WishboneMasterAdapter
from coreblocks.peripherals.wishbone import WishboneMaster, WishboneInterface
from coreblocks.cache.refiller import SimpleCommonBusCacheRefiller
from coreblocks.frontend.fetch import Fetch, UnalignedFetch
from coreblocks.frontend.fetch.fetch import Fetch, UnalignedFetch
from transactron.lib.transformers import MethodMap, MethodProduct
from transactron.lib import BasicFifo
from transactron.lib.metrics import HwMetricsEnabledKey
Expand Down
File renamed without changes.
Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
from amaranth import *
from transactron import Method, def_method, TModule
from coreblocks.params import RATLayouts, GenParams
from coreblocks.interface.layouts import RATLayouts
from coreblocks.params import GenParams

__all__ = ["FRAT", "RRAT"]

Expand Down
Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
from amaranth import *
from transactron import Method, def_method, TModule
from coreblocks.params import RFLayouts, GenParams
from coreblocks.interface.layouts import RFLayouts
from coreblocks.params import GenParams
from transactron.utils.transactron_helpers import make_layout

__all__ = ["RegisterFile"]
Expand Down
Original file line number Diff line number Diff line change
@@ -1,7 +1,8 @@
from amaranth import *
from transactron import Method, def_method, TModule
from transactron.lib.metrics import *
from ..params import GenParams, ROBLayouts
from coreblocks.interface.layouts import ROBLayouts
from coreblocks.params import GenParams

__all__ = ["ReorderBuffer"]

Expand Down
2 changes: 2 additions & 0 deletions coreblocks/frontend/decoder/__init__.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,2 @@
from .isa import * # noqa: F401
from .optypes import * # noqa: F401
Original file line number Diff line number Diff line change
@@ -1,10 +1,10 @@
from amaranth import *

from coreblocks.params.isa import Funct3
from coreblocks.params.optypes import OpType
from coreblocks.frontend.decoder.isa import Funct3
from coreblocks.frontend.decoder.optypes import OpType
from transactron.lib.metrics import *
from transactron import Method, Transaction, TModule
from ..params import GenParams
from coreblocks.params import GenParams
from .instr_decoder import InstrDecoder
from coreblocks.params import *

Expand Down
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