Move tests/common to transactron (#569)

test/cache/test_icache.py

@@ -14,7 +14,7 @@
 from coreblocks.params.configurations import test_core_config
 from coreblocks.cache.refiller import SimpleCommonBusCacheRefiller
 
-from ..common import TestCaseWithSimulator, TestbenchIO, def_method_mock, RecordIntDictRet
+from transactron.testing import TestCaseWithSimulator, TestbenchIO, def_method_mock, RecordIntDictRet
 from ..peripherals.test_wishbone import WishboneInterfaceWrapper
 
 

test/frontend/test_decode_stage.py

@@ -1,6 +1,6 @@
 from transactron.lib import AdapterTrans, FIFO
 
-from ..common import TestCaseWithSimulator, TestbenchIO, SimpleTestCircuit, ModuleConnector
+from transactron.testing import TestCaseWithSimulator, TestbenchIO, SimpleTestCircuit, ModuleConnector
 
 from coreblocks.frontend.decode_stage import DecodeStage
 from coreblocks.params import GenParams, FetchLayouts, DecodeLayouts, OpType, Funct3, Funct7

test/frontend/test_fetch.py

@@ -12,7 +12,7 @@
 from coreblocks.params import *
 from coreblocks.params.configurations import test_core_config
 from transactron.utils import ModuleConnector
-from ..common import TestCaseWithSimulator, TestbenchIO, def_method_mock, SimpleTestCircuit
+from transactron.testing import TestCaseWithSimulator, TestbenchIO, def_method_mock, SimpleTestCircuit
 
 
 class MockedICache(Elaboratable, CacheInterface):

test/frontend/test_instr_decoder.py

@@ -1,6 +1,6 @@
 from amaranth.sim import *
 
-from ..common import TestCaseWithSimulator
+from transactron.testing import TestCaseWithSimulator
 
 from coreblocks.params import *
 from coreblocks.params.configurations import test_core_config

test/frontend/test_rvc.py

@@ -8,7 +8,7 @@
 from coreblocks.params.configurations import test_core_config
 from transactron.utils import ValueLike
 
-from ..common import TestCaseWithSimulator
+from transactron.testing import TestCaseWithSimulator
 
 COMMON_TESTS = [
     # Illegal instruction

test/fu/functional_common.py

@@ -16,7 +16,7 @@
 from coreblocks.params.layouts import ExceptionRegisterLayouts
 from coreblocks.params.optypes import OpType
 from transactron.lib import Adapter
-from test.common import RecordIntDict, RecordIntDictRet, TestbenchIO, TestCaseWithSimulator, SimpleTestCircuit
+from transactron.testing import RecordIntDict, RecordIntDictRet, TestbenchIO, TestCaseWithSimulator, SimpleTestCircuit
 from transactron.utils import ModuleConnector
 
 

test/fu/test_fu_decoder.py

@@ -3,7 +3,7 @@
 from amaranth import *
 from amaranth.sim import *
 
-from ..common import SimpleTestCircuit, TestCaseWithSimulator
+from transactron.testing import SimpleTestCircuit, TestCaseWithSimulator
 
 from coreblocks.fu.fu_decoder import DecoderManager, Decoder
 from coreblocks.params import OpType, Funct3, Funct7, GenParams

test/fu/test_unsigned_mul_unit.py

@@ -10,7 +10,7 @@
 from coreblocks.fu.unsigned_multiplication.sequence import SequentialUnsignedMul
 from coreblocks.fu.unsigned_multiplication.shift import ShiftUnsignedMul
 
-from test.common import TestCaseWithSimulator, SimpleTestCircuit
+from transactron.testing import TestCaseWithSimulator, SimpleTestCircuit
 
 from coreblocks.params import GenParams
 from coreblocks.params.configurations import test_core_config

test/lsu/test_dummylsu.py

@@ -14,8 +14,8 @@
 from transactron.utils.dependencies import DependencyManager
 from coreblocks.params.layouts import ExceptionRegisterLayouts
 from coreblocks.peripherals.wishbone import *
+from transactron.testing import TestbenchIO, TestCaseWithSimulator, def_method_mock
 from coreblocks.peripherals.bus_adapter import WishboneMasterAdapter
-from test.common import TestbenchIO, TestCaseWithSimulator, def_method_mock
 from test.peripherals.test_wishbone import WishboneInterfaceWrapper
 
 

test/lsu/test_pma.py

@@ -10,8 +10,8 @@
 from transactron.utils.dependencies import DependencyManager
 from coreblocks.params.layouts import ExceptionRegisterLayouts
 from coreblocks.peripherals.wishbone import *
+from transactron.testing import TestbenchIO, TestCaseWithSimulator, def_method_mock
 from coreblocks.peripherals.bus_adapter import WishboneMasterAdapter
-from test.common import TestbenchIO, TestCaseWithSimulator, def_method_mock
 from test.peripherals.test_wishbone import WishboneInterfaceWrapper
 
 

test/peripherals/test_axi_lite.py

@@ -2,7 +2,7 @@
 from transactron import Method, def_method, TModule
 from transactron.lib import AdapterTrans
 
-from ..common import *
+from transactron.testing import *
 
 
 class AXILiteInterfaceWrapper:

test/peripherals/test_wishbone.py

@@ -5,7 +5,7 @@
 
 from transactron.lib import AdapterTrans
 
-from ..common import *
+from transactron.testing import *
 
 
 class WishboneInterfaceWrapper:

test/regression/pysim.py

@@ -4,7 +4,7 @@
 from .memory import *
 from .common import SimulationBackend, SimulationExecutionResult
 
-from ..common import SimpleTestCircuit, PysimSimulator
+from transactron.testing import SimpleTestCircuit, PysimSimulator
 from ..peripherals.test_wishbone import WishboneInterfaceWrapper
 
 from coreblocks.core import Core

test/scheduler/test_rs_selection.py

@@ -8,7 +8,7 @@
 from coreblocks.params.configurations import test_core_config
 from coreblocks.scheduler.scheduler import RSSelection
 from transactron.lib import FIFO, Adapter, AdapterTrans
-from test.common import TestCaseWithSimulator, TestbenchIO
+from transactron.testing import TestCaseWithSimulator, TestbenchIO
 
 _rs1_optypes = {OpType.ARITHMETIC, OpType.COMPARE}
 _rs2_optypes = {OpType.LOGIC, OpType.COMPARE}

test/scheduler/test_scheduler.py

@@ -19,7 +19,7 @@
 from coreblocks.params.configurations import test_core_config
 from coreblocks.structs_common.rob import ReorderBuffer
 from coreblocks.utils.protocols import FuncBlock
-from ..common import RecordIntDict, TestCaseWithSimulator, TestGen, TestbenchIO, def_method_mock
+from transactron.testing import RecordIntDict, TestCaseWithSimulator, TestGen, TestbenchIO, def_method_mock
 
 
 class SchedulerTestCircuit(Elaboratable):

test/scheduler/test_wakeup_select.py

@@ -15,7 +15,7 @@
 from transactron.lib import Adapter
 from coreblocks.scheduler.wakeup_select import *
 
-from ..common import RecordIntDict, TestCaseWithSimulator, TestbenchIO
+from transactron.testing import RecordIntDict, TestCaseWithSimulator, TestbenchIO
 
 
 class WakeupTestCircuit(Elaboratable):

test/stages/test_backend.py

@@ -8,7 +8,7 @@
 from coreblocks.params.layouts import *
 from coreblocks.params import GenParams
 from coreblocks.params.configurations import test_core_config
-from ..common import TestCaseWithSimulator, TestbenchIO
+from transactron.testing import TestCaseWithSimulator, TestbenchIO
 
 
 class BackendTestCircuit(Elaboratable):

test/stages/test_retirement.py

@@ -7,7 +7,7 @@
 from coreblocks.params import ROBLayouts, RFLayouts, GenParams, LSULayouts, SchedulerLayouts
 from coreblocks.params.configurations import test_core_config
 
-from ..common import *
+from transactron.testing import *
 from collections import deque
 import random
 

test/structs_common/test_csr.py

@@ -10,7 +10,7 @@
 from transactron.utils.dependencies import DependencyManager
 from coreblocks.params.optypes import OpType
 
-from ..common import *
+from transactron.testing import *
 
 import random
 

test/structs_common/test_exception.py

@@ -8,7 +8,7 @@
 from transactron.lib import Adapter
 from transactron.utils import ModuleConnector
 
-from ..common import *
+from transactron.testing import *
 
 import random
 

test/structs_common/test_rat.py

@@ -1,4 +1,4 @@
-from ..common import TestCaseWithSimulator, SimpleTestCircuit
+from transactron.testing import TestCaseWithSimulator, SimpleTestCircuit
 
 from coreblocks.structs_common.rat import FRAT, RRAT
 from coreblocks.params import GenParams

test/structs_common/test_reorder_buffer.py

@@ -1,6 +1,6 @@
 from amaranth.sim import Passive, Settle
 
-from ..common import TestCaseWithSimulator, SimpleTestCircuit
+from transactron.testing import TestCaseWithSimulator, SimpleTestCircuit
 
 from coreblocks.structs_common.rob import ReorderBuffer
 from coreblocks.params import GenParams

test/structs_common/test_rs.py

@@ -1,6 +1,6 @@
 from amaranth.sim import Settle
 
-from ..common import TestCaseWithSimulator, get_outputs, SimpleTestCircuit
+from transactron.testing import TestCaseWithSimulator, get_outputs, SimpleTestCircuit
 
 from coreblocks.structs_common.rs import RS
 from coreblocks.params import *

test/test_core.py

@@ -3,7 +3,7 @@
 from transactron.lib import AdapterTrans
 from transactron.utils import align_to_power_of_two, signed_to_int
 
-from .common import TestCaseWithSimulator, TestbenchIO
+from transactron.testing import TestCaseWithSimulator, TestbenchIO
 
 from coreblocks.core import Core
 from coreblocks.params import GenParams

test/transactions/test_adapter.py

@@ -3,7 +3,7 @@
 from transactron import Method, def_method, TModule
 
 
-from ..common import TestCaseWithSimulator, data_layout, SimpleTestCircuit, ModuleConnector
+from transactron.testing import TestCaseWithSimulator, data_layout, SimpleTestCircuit, ModuleConnector
 
 
 class Echo(Elaboratable):

test/transactions/test_branches.py

@@ -11,7 +11,7 @@
     def_method,
 )
 from unittest import TestCase
-from ..common import TestCaseWithSimulator
+from transactron.testing import TestCaseWithSimulator
 
 
 class TestExclusivePath(TestCase):

test/transactions/test_methods.py

@@ -2,7 +2,7 @@
 from amaranth import *
 from amaranth.sim import *
 
-from ..common import TestCaseWithSimulator, TestbenchIO, data_layout
+from transactron.testing import TestCaseWithSimulator, TestbenchIO, data_layout
 
 from transactron import *
 from transactron.utils import MethodStruct

test/transactions/test_simultaneous.py

@@ -5,7 +5,7 @@
 
 from transactron.utils import ModuleConnector
 
-from ..common import SimpleTestCircuit, TestCaseWithSimulator, TestbenchIO, def_method_mock
+from transactron.testing import SimpleTestCircuit, TestCaseWithSimulator, TestbenchIO, def_method_mock
 
 from transactron import *
 from transactron.lib import Adapter, Connect, ConnectTrans

test/transactions/test_transaction_lib.py

@@ -15,7 +15,7 @@
 from coreblocks.utils import *
 from transactron.utils._typing import ModuleLike, MethodStruct
 from transactron.utils import ModuleConnector
-from ..common import (
+from transactron.testing import (
     SimpleTestCircuit,
     TestCaseWithSimulator,
     TestbenchIO,

test/transactions/test_transactions.py

@@ -9,7 +9,7 @@
 from typing import Iterable, Callable
 from parameterized import parameterized, parameterized_class
 
-from ..common import TestCaseWithSimulator, TestbenchIO, data_layout
+from transactron.testing import TestCaseWithSimulator, TestbenchIO, data_layout
 
 from transactron import *
 from transactron.lib import Adapter, AdapterTrans

test/common/_test/test_infrastructure.py → test/transactron/testing/test_infrastructure.py

@@ -1,5 +1,5 @@
 from amaranth import *
-from test.common import *
+from transactron.testing import *
 
 
 class EmptyCircuit(Elaboratable):

test/utils/test_fifo.py

@@ -3,7 +3,7 @@
 
 from transactron.lib import AdapterTrans, BasicFifo
 
-from test.common import TestCaseWithSimulator, TestbenchIO, data_layout
+from transactron.testing import TestCaseWithSimulator, TestbenchIO, data_layout
 from collections import deque
 from parameterized import parameterized_class
 import random

test/utils/test_onehotswitch.py

@@ -3,7 +3,7 @@
 
 from transactron.utils import OneHotSwitch
 
-from test.common import TestCaseWithSimulator
+from transactron.testing import TestCaseWithSimulator
 
 from parameterized import parameterized
 

test/utils/test_utils.py

@@ -2,7 +2,7 @@
 import random
 
 from amaranth import *
-from test.common import *
+from transactron.testing import *
 from transactron.utils import (
     align_to_power_of_two,
     align_down_to_power_of_two,

test/common/infrastructure.py → transactron/testing/infrastructure.py

@@ -11,7 +11,7 @@
 from .testbenchio import TestbenchIO
 from .profiler import profiler_process, Profile
 from .functions import TestGen
-from ..gtkw_extension import write_vcd_ext
+from .gtkw_extension import write_vcd_ext
 from transactron import Method
 from transactron.lib import AdapterTrans
 from transactron.core import TransactionModule