Add adapter module for bus (#566)

_sources/coreblocks.peripherals.rst.txt

@@ -12,6 +12,14 @@ coreblocks.peripherals.axi\_lite module
    :undoc-members:
    :show-inheritance:
 
+coreblocks.peripherals.bus\_adapter module
+------------------------------------------
+
+.. automodule:: coreblocks.peripherals.bus_adapter
+   :members:
+   :undoc-members:
+   :show-inheritance:
+
 coreblocks.peripherals.wishbone module
 --------------------------------------
 

api.html

@@ -149,6 +149,7 @@ <h2>coreblocks<a class="headerlink" href="#coreblocks" title="Permalink to this
 <li class="toctree-l3"><a class="reference internal" href="coreblocks.peripherals.html">coreblocks.peripherals package</a><ul>
 <li class="toctree-l4"><a class="reference internal" href="coreblocks.peripherals.html#submodules">Submodules</a></li>
 <li class="toctree-l4"><a class="reference internal" href="coreblocks.peripherals.html#module-coreblocks.peripherals.axi_lite">coreblocks.peripherals.axi_lite module</a></li>
+<li class="toctree-l4"><a class="reference internal" href="coreblocks.peripherals.html#module-coreblocks.peripherals.bus_adapter">coreblocks.peripherals.bus_adapter module</a></li>
 <li class="toctree-l4"><a class="reference internal" href="coreblocks.peripherals.html#module-coreblocks.peripherals.wishbone">coreblocks.peripherals.wishbone module</a></li>
 <li class="toctree-l4"><a class="reference internal" href="coreblocks.peripherals.html#module-coreblocks.peripherals">Module contents</a></li>
 </ul>
@@ -258,7 +259,7 @@ <h2>transactron<a class="headerlink" href="#transactron" title="Permalink to thi
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 09:21 2024-01-29.
+      <span class="lastupdated">Last updated on 13:31 2024-01-29.
       </span></p>
   </div>
 

assumptions.html

@@ -104,7 +104,7 @@ <h1>List of assumptions made during development<a class="headerlink" href="#list
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 09:21 2024-01-29.
+      <span class="lastupdated">Last updated on 13:31 2024-01-29.
       </span></p>
   </div>
 

components/icache.html

@@ -131,7 +131,7 @@ <h2>Address mapping example<a class="headerlink" href="#address-mapping-example"
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 09:21 2024-01-29.
+      <span class="lastupdated">Last updated on 13:31 2024-01-29.
       </span></p>
   </div>
 

coreblocks.frontend.html

@@ -228,7 +228,7 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 <dd><p>Bases: <code class="xref py py-class docutils literal notranslate"><span class="pre">Elaboratable</span></code>, <a class="reference internal" href="#coreblocks.frontend.icache.ICacheInterface" title="coreblocks.frontend.icache.ICacheInterface"><code class="xref py py-class docutils literal notranslate"><span class="pre">ICacheInterface</span></code></a></p>
 <dl class="py method">
 <dt class="sig sig-object py" id="coreblocks.frontend.icache.ICacheBypass.__init__">
-<span class="sig-name descname"><span class="pre">__init__</span></span><span class="sig-paren">(</span><em class="sig-param"><span class="n"><span class="pre">layouts</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><a class="reference internal" href="coreblocks.params.html#coreblocks.params.layouts.ICacheLayouts" title="coreblocks.params.layouts.ICacheLayouts"><span class="pre">ICacheLayouts</span></a></span></em>, <em class="sig-param"><span class="n"><span class="pre">params</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><a class="reference internal" href="coreblocks.params.html#coreblocks.params.icache_params.ICacheParameters" title="coreblocks.params.icache_params.ICacheParameters"><span class="pre">ICacheParameters</span></a></span></em>, <em class="sig-param"><span class="n"><span class="pre">wb_master</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><a class="reference internal" href="coreblocks.peripherals.html#coreblocks.peripherals.wishbone.WishboneMaster" title="coreblocks.peripherals.wishbone.WishboneMaster"><span class="pre">WishboneMaster</span></a></span></em><span class="sig-paren">)</span> <span class="sig-return"><span class="sig-return-icon">&#x2192;</span> <span class="sig-return-typehint"><span class="pre">None</span></span></span><a class="headerlink" href="#coreblocks.frontend.icache.ICacheBypass.__init__" title="Permalink to this definition"></a></dt>
+<span class="sig-name descname"><span class="pre">__init__</span></span><span class="sig-paren">(</span><em class="sig-param"><span class="n"><span class="pre">layouts</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><a class="reference internal" href="coreblocks.params.html#coreblocks.params.layouts.ICacheLayouts" title="coreblocks.params.layouts.ICacheLayouts"><span class="pre">ICacheLayouts</span></a></span></em>, <em class="sig-param"><span class="n"><span class="pre">params</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><a class="reference internal" href="coreblocks.params.html#coreblocks.params.icache_params.ICacheParameters" title="coreblocks.params.icache_params.ICacheParameters"><span class="pre">ICacheParameters</span></a></span></em>, <em class="sig-param"><span class="n"><span class="pre">bus_master</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><a class="reference internal" href="coreblocks.peripherals.html#coreblocks.peripherals.bus_adapter.BusMasterInterface" title="coreblocks.peripherals.bus_adapter.BusMasterInterface"><span class="pre">BusMasterInterface</span></a></span></em><span class="sig-paren">)</span> <span class="sig-return"><span class="sig-return-icon">&#x2192;</span> <span class="sig-return-typehint"><span class="pre">None</span></span></span><a class="headerlink" href="#coreblocks.frontend.icache.ICacheBypass.__init__" title="Permalink to this definition"></a></dt>
 <dd></dd></dl>
 
 </dd></dl>
@@ -268,12 +268,12 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 </dd></dl>
 
 <dl class="py class">
-<dt class="sig sig-object py" id="coreblocks.frontend.icache.SimpleWBCacheRefiller">
-<em class="property"><span class="pre">class</span><span class="w"> </span></em><span class="sig-prename descclassname"><span class="pre">coreblocks.frontend.icache.</span></span><span class="sig-name descname"><span class="pre">SimpleWBCacheRefiller</span></span><a class="headerlink" href="#coreblocks.frontend.icache.SimpleWBCacheRefiller" title="Permalink to this definition"></a></dt>
+<dt class="sig sig-object py" id="coreblocks.frontend.icache.SimpleCommonBusCacheRefiller">
+<em class="property"><span class="pre">class</span><span class="w"> </span></em><span class="sig-prename descclassname"><span class="pre">coreblocks.frontend.icache.</span></span><span class="sig-name descname"><span class="pre">SimpleCommonBusCacheRefiller</span></span><a class="headerlink" href="#coreblocks.frontend.icache.SimpleCommonBusCacheRefiller" title="Permalink to this definition"></a></dt>
 <dd><p>Bases: <code class="xref py py-class docutils literal notranslate"><span class="pre">Elaboratable</span></code>, <code class="xref py py-class docutils literal notranslate"><span class="pre">CacheRefillerInterface</span></code></p>
 <dl class="py method">
-<dt class="sig sig-object py" id="coreblocks.frontend.icache.SimpleWBCacheRefiller.__init__">
-<span class="sig-name descname"><span class="pre">__init__</span></span><span class="sig-paren">(</span><em class="sig-param"><span class="n"><span class="pre">layouts</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><a class="reference internal" href="coreblocks.params.html#coreblocks.params.layouts.ICacheLayouts" title="coreblocks.params.layouts.ICacheLayouts"><span class="pre">ICacheLayouts</span></a></span></em>, <em class="sig-param"><span class="n"><span class="pre">params</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><a class="reference internal" href="coreblocks.params.html#coreblocks.params.icache_params.ICacheParameters" title="coreblocks.params.icache_params.ICacheParameters"><span class="pre">ICacheParameters</span></a></span></em>, <em class="sig-param"><span class="n"><span class="pre">wb_master</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><a class="reference internal" href="coreblocks.peripherals.html#coreblocks.peripherals.wishbone.WishboneMaster" title="coreblocks.peripherals.wishbone.WishboneMaster"><span class="pre">WishboneMaster</span></a></span></em><span class="sig-paren">)</span><a class="headerlink" href="#coreblocks.frontend.icache.SimpleWBCacheRefiller.__init__" title="Permalink to this definition"></a></dt>
+<dt class="sig sig-object py" id="coreblocks.frontend.icache.SimpleCommonBusCacheRefiller.__init__">
+<span class="sig-name descname"><span class="pre">__init__</span></span><span class="sig-paren">(</span><em class="sig-param"><span class="n"><span class="pre">layouts</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><a class="reference internal" href="coreblocks.params.html#coreblocks.params.layouts.ICacheLayouts" title="coreblocks.params.layouts.ICacheLayouts"><span class="pre">ICacheLayouts</span></a></span></em>, <em class="sig-param"><span class="n"><span class="pre">params</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><a class="reference internal" href="coreblocks.params.html#coreblocks.params.icache_params.ICacheParameters" title="coreblocks.params.icache_params.ICacheParameters"><span class="pre">ICacheParameters</span></a></span></em>, <em class="sig-param"><span class="n"><span class="pre">bus_master</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><a class="reference internal" href="coreblocks.peripherals.html#coreblocks.peripherals.bus_adapter.BusMasterInterface" title="coreblocks.peripherals.bus_adapter.BusMasterInterface"><span class="pre">BusMasterInterface</span></a></span></em><span class="sig-paren">)</span><a class="headerlink" href="#coreblocks.frontend.icache.SimpleCommonBusCacheRefiller.__init__" title="Permalink to this definition"></a></dt>
 <dd></dd></dl>
 
 </dd></dl>
@@ -472,7 +472,7 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 09:21 2024-01-29.
+      <span class="lastupdated">Last updated on 13:31 2024-01-29.
       </span></p>
   </div>
 

coreblocks.fu.html

@@ -965,7 +965,7 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 09:21 2024-01-29.
+      <span class="lastupdated">Last updated on 13:31 2024-01-29.
       </span></p>
   </div>
 

coreblocks.fu.unsigned_multiplication.html

@@ -237,7 +237,7 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 09:21 2024-01-29.
+      <span class="lastupdated">Last updated on 13:31 2024-01-29.
       </span></p>
   </div>
 

coreblocks.html

@@ -149,6 +149,7 @@ <h2>Subpackages<a class="headerlink" href="#subpackages" title="Permalink to thi
 <li class="toctree-l1"><a class="reference internal" href="coreblocks.peripherals.html">coreblocks.peripherals package</a><ul>
 <li class="toctree-l2"><a class="reference internal" href="coreblocks.peripherals.html#submodules">Submodules</a></li>
 <li class="toctree-l2"><a class="reference internal" href="coreblocks.peripherals.html#module-coreblocks.peripherals.axi_lite">coreblocks.peripherals.axi_lite module</a></li>
+<li class="toctree-l2"><a class="reference internal" href="coreblocks.peripherals.html#module-coreblocks.peripherals.bus_adapter">coreblocks.peripherals.bus_adapter module</a></li>
 <li class="toctree-l2"><a class="reference internal" href="coreblocks.peripherals.html#module-coreblocks.peripherals.wishbone">coreblocks.peripherals.wishbone module</a></li>
 <li class="toctree-l2"><a class="reference internal" href="coreblocks.peripherals.html#module-coreblocks.peripherals">Module contents</a></li>
 </ul>
@@ -226,7 +227,7 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 09:21 2024-01-29.
+      <span class="lastupdated">Last updated on 13:31 2024-01-29.
       </span></p>
   </div>
 

coreblocks.lsu.html

@@ -137,13 +137,13 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 </dl>
 <dl class="py method">
 <dt class="sig sig-object py" id="coreblocks.lsu.dummyLsu.LSUDummy.__init__">
-<span class="sig-name descname"><span class="pre">__init__</span></span><span class="sig-paren">(</span><em class="sig-param"><span class="n"><span class="pre">gen_params</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><a class="reference internal" href="coreblocks.params.html#coreblocks.params.genparams.GenParams" title="coreblocks.params.genparams.GenParams"><span class="pre">GenParams</span></a></span></em>, <em class="sig-param"><span class="n"><span class="pre">bus</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><a class="reference internal" href="coreblocks.peripherals.html#coreblocks.peripherals.wishbone.WishboneMaster" title="coreblocks.peripherals.wishbone.WishboneMaster"><span class="pre">WishboneMaster</span></a></span></em><span class="sig-paren">)</span> <span class="sig-return"><span class="sig-return-icon">&#x2192;</span> <span class="sig-return-typehint"><span class="pre">None</span></span></span><a class="headerlink" href="#coreblocks.lsu.dummyLsu.LSUDummy.__init__" title="Permalink to this definition"></a></dt>
+<span class="sig-name descname"><span class="pre">__init__</span></span><span class="sig-paren">(</span><em class="sig-param"><span class="n"><span class="pre">gen_params</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><a class="reference internal" href="coreblocks.params.html#coreblocks.params.genparams.GenParams" title="coreblocks.params.genparams.GenParams"><span class="pre">GenParams</span></a></span></em>, <em class="sig-param"><span class="n"><span class="pre">bus</span></span><span class="p"><span class="pre">:</span></span><span class="w"> </span><span class="n"><a class="reference internal" href="coreblocks.peripherals.html#coreblocks.peripherals.bus_adapter.BusMasterInterface" title="coreblocks.peripherals.bus_adapter.BusMasterInterface"><span class="pre">BusMasterInterface</span></a></span></em><span class="sig-paren">)</span> <span class="sig-return"><span class="sig-return-icon">&#x2192;</span> <span class="sig-return-typehint"><span class="pre">None</span></span></span><a class="headerlink" href="#coreblocks.lsu.dummyLsu.LSUDummy.__init__" title="Permalink to this definition"></a></dt>
 <dd><dl class="field-list simple">
 <dt class="field-odd">Parameters</dt>
 <dd class="field-odd"><dl class="simple">
 <dt><strong>gen_params</strong><span class="classifier">GenParams</span></dt><dd><p>Parameters to be used during processor generation.</p>
 </dd>
-<dt><strong>bus</strong><span class="classifier">WishboneMaster</span></dt><dd><p>An instance of the Wishbone master for interfacing with the data bus.</p>
+<dt><strong>bus</strong><span class="classifier">BusMasterInterface</span></dt><dd><p>An instance of the bus master for interfacing with the data bus.</p>
 </dd>
 </dl>
 </dd>
@@ -236,7 +236,7 @@ <h2>Submodules<a class="headerlink" href="#submodules" title="Permalink to this
 
   <div role="contentinfo">
     <p>&#169; Copyright Kuźnia Rdzeni, 2024.
-      <span class="lastupdated">Last updated on 09:21 2024-01-29.
+      <span class="lastupdated">Last updated on 13:31 2024-01-29.
       </span></p>
   </div>