Allow parallel compilation of the verilated model (#623)

kuznia-rdzeni · Mar 21, 2024 · 29e522a · 29e522a
1 parent b7df72a
commit 29e522a
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diff --git a/test/regression/cocotb/benchmark.Makefile b/test/regression/cocotb/benchmark.Makefile
@@ -15,6 +15,7 @@ SIM_BUILD = build/benchmark
 # Yosys/Amaranth borkedness workaround
 ifeq ($(SIM),verilator)
   EXTRA_ARGS += -Wno-CASEINCOMPLETE -Wno-CASEOVERLAP -Wno-WIDTHEXPAND -Wno-WIDTHTRUNC
+  BUILD_ARGS += -j`nproc`
 endif
 
 ifeq ($(TRACES),1)

diff --git a/test/regression/cocotb/signature.Makefile b/test/regression/cocotb/signature.Makefile
@@ -15,6 +15,7 @@ SIM_BUILD = build/signature
 # Yosys/Amaranth borkedness workaround
 ifeq ($(SIM),verilator)
   EXTRA_ARGS += -Wno-CASEINCOMPLETE -Wno-CASEOVERLAP -Wno-WIDTHEXPAND -Wno-WIDTHTRUNC
+  BUILD_ARGS += -j`nproc`
 endif
 
 ifeq ($(TRACES),1)

diff --git a/test/regression/cocotb/test.Makefile b/test/regression/cocotb/test.Makefile
@@ -15,6 +15,7 @@ SIM_BUILD = build/test
 # Yosys/Amaranth borkedness workaround
 ifeq ($(SIM),verilator)
   EXTRA_ARGS += -Wno-CASEINCOMPLETE -Wno-CASEOVERLAP -Wno-WIDTHEXPAND -Wno-WIDTHTRUNC
+  BUILD_ARGS += -j`nproc`
 endif
 
 ifeq ($(TRACES),1)