Simplify code

kuznia-rdzeni · Feb 11, 2024 · 2319b0c · 2319b0c
1 parent 2e60114
commit 2319b0c
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Showing 3 changed files with 3 additions and 6 deletions.
diff --git a/scripts/gen_verilog.py b/scripts/gen_verilog.py
@@ -45,8 +45,7 @@ def elaborate(self, platform: Platform):
 
 
 def gen_verilog(core_config: CoreConfiguration, output_path):
-    dependency_manager = DependencyManager()
-    with DependencyContext(dependency_manager):
+    with DependencyContext(DependencyManager()):
         top = Top(GenParams(core_config))
 
         with open(output_path, "w") as f:

diff --git a/scripts/synthesize.py b/scripts/synthesize.py
@@ -139,8 +139,7 @@ def unit(gen_params: GenParams):
 
 
 def synthesize(core_config: CoreConfiguration, platform: str, core: UnitCore):
-    dependency_manager = DependencyManager()
-    with DependencyContext(dependency_manager):
+    with DependencyContext(DependencyManager()):
         gen_params = GenParams(core_config)
         resource_builder, module = core(gen_params)
 

diff --git a/test/regression/pysim.py b/test/regression/pysim.py
@@ -91,8 +91,7 @@ def f():
         return f
 
     async def run(self, mem_model: CoreMemoryModel, timeout_cycles: int = 5000) -> SimulationExecutionResult:
-        self.dependency_manager = DependencyManager()
-        with DependencyContext(self.dependency_manager):
+        with DependencyContext(DependencyManager()):
             wb_instr_bus = WishboneBus(self.gp.wb_params)
             wb_data_bus = WishboneBus(self.gp.wb_params)
             core = Core(gen_params=self.gp, wb_instr_bus=wb_instr_bus, wb_data_bus=wb_data_bus)